diff options
| author | V Sowmya <v.sowmya@intel.com> | 2020-11-30 19:49:16 +0530 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2020-12-01 15:27:01 +0000 |
| commit | a99f61fec41f22c6c518d53078c322ca9891884c (patch) | |
| tree | 131c88e91501f8c62618a492a2790b1a30aed3df /src/mainboard/intel | |
| parent | e2ce56928c11417114906a1dae2b12a3977bd39e (diff) | |
mb/intel/jslrvp: Modify the flash layout for fsp debug build
Current flash layout doesn't support the fsp debug builds since
the FW_MAIN_A/B doesn't have enough space to hold the fsp debug
binaries along with ME RW binaries.
This patch reduces the SI_ALL size to 3.5MiB and increase the
SI_BIOS to 12.5MiB to include both ME RW and FSP debug binaries.
BRANCH=dedede
TEST=Build and Boot jslrvp with fsp debug enabled coreboot.
Cq-Depend: chrome-internal:3425366
Change-Id: I6f6354b0c80791f626c09dabafe33eefccedb9c2
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48154
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Maulik V Vaghela <maulik.v.vaghela@intel.com>
Reviewed-by: Ronak Kanabar <ronak.kanabar@intel.com>
Reviewed-by: Karthik Ramasubramanian <kramasub@google.com>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/jasperlake_rvp/chromeos.fmd | 49 |
1 files changed, 25 insertions, 24 deletions
diff --git a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd index 57be7f19e9..e4e0b242e0 100644 --- a/src/mainboard/intel/jasperlake_rvp/chromeos.fmd +++ b/src/mainboard/intel/jasperlake_rvp/chromeos.fmd @@ -1,37 +1,38 @@ FLASH@0xff000000 0x1000000 { - SI_ALL@0x0 0x600000 { + SI_ALL@0x0 0x381000 { SI_DESC@0x0 0x1000 SI_EC@0x1000 0x80000 - SI_ME@0x81000 0x57F000 + SI_ME@0x81000 0x300000 } - SI_BIOS@0x600000 0xA00000 { - RW_SECTION_A@0x0 0x2d0000 { - VBLOCK_A@0x0 0x10000 - FW_MAIN_A(CBFS)@0x10000 0x12ffc0 - RW_FWID_A@0x13ffc0 0x40 - ME_RW_A(CBFS)@0x140000 0x190000 + SI_BIOS@0x381000 0xc7f000 { + RW_LEGACY(CBFS)@0x0 0x100000 + RW_SECTION_A@0x100000 0x3a4800 { + VBLOCK_A@0x0 0x2000 + FW_MAIN_A(CBFS)@0x2000 0x2127c0 + RW_FWID_A@0x2147c0 0x40 + ME_RW_A(CBFS)@0x214800 0x190000 } - RW_SECTION_B@0x2d0000 0x2d0000 { - VBLOCK_B@0x0 0x10000 - FW_MAIN_B(CBFS)@0x10000 0x12ffc0 - RW_FWID_B@0x13ffc0 0x40 - ME_RW_B(CBFS)@0x140000 0x190000 + RW_SECTION_B@0x4a4800 0x3a4800 { + VBLOCK_B@0x0 0x2000 + FW_MAIN_B(CBFS)@0x2000 0x2127c0 + RW_FWID_B@0x2147c0 0x40 + ME_RW_B(CBFS)@0x214800 0x190000 } - RW_MISC@0x5a0000 0x30000 { - UNIFIED_MRC_CACHE@0x0 0x20000 { + RW_MISC@0x849000 0x36000 { + UNIFIED_MRC_CACHE(PRESERVE)@0x0 0x30000 { RECOVERY_MRC_CACHE@0x0 0x10000 - RW_MRC_CACHE@0x10000 0x10000 + RW_MRC_CACHE@0x10000 0x20000 } - RW_ELOG(PRESERVE)@0x20000 0x4000 - RW_SHARED@0x24000 0x4000 { - SHARED_DATA@0x0 0x2000 - VBLOCK_DEV@0x2000 0x2000 + RW_ELOG(PRESERVE)@0x30000 0x1000 + RW_SHARED@0x31000 0x1000 { + SHARED_DATA@0x0 0x1000 } - RW_VPD(PRESERVE)@0x28000 0x2000 - RW_NVRAM(PRESERVE)@0x2a000 0x6000 + RW_VPD(PRESERVE)@0x32000 0x2000 + RW_NVRAM(PRESERVE)@0x34000 0x2000 } - RW_LEGACY(CBFS)@0x5d0000 0x30000 - WP_RO@0x600000 0x400000 { + # Make WP_RO region align with SPI vendor + # memory protected range specification. + WP_RO@0x87f000 0x400000 { RO_VPD(PRESERVE)@0x0 0x4000 RO_SECTION@0x4000 0x3fc000 { FMAP@0x0 0x800 |