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authorSubrata Banik <subrata.banik@intel.com>2021-01-09 16:38:34 +0530
committerSubrata Banik <subrata.banik@intel.com>2021-01-10 17:49:27 +0000
commit8c4aa15e91a6149f51d03463d025ec6bf614397d (patch)
tree9ec82c6edf9089741474cc6e9a34963045f51708 /src/mainboard/intel
parent85144d9002d6a712ce793b87e739f613080fcc4a (diff)
mb/intel/adlrvp: Fix FW download failed for PEG 060, 010
Enable PCIE RP1 to fix DEKEL FW download failed for x4 controller (PEG 0:6:0). Enable PCIE RP3 to fix HSPHY FW download failed for x8 controller (PEG 0:1:0) BUG=b:176940923 TEST=No FSP error seen while loading DEKEL, HSPHY FW. Change-Id: I3cd8cba02a96185803a0c0d442f3d6aa495d2642 Signed-off-by: Subrata Banik <subrata.banik@intel.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49100 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/adlrvp/devicetree.cb10
1 files changed, 8 insertions, 2 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb
index 51b781c619..cf9afaf68c 100644
--- a/src/mainboard/intel/adlrvp/devicetree.cb
+++ b/src/mainboard/intel/adlrvp/devicetree.cb
@@ -80,6 +80,12 @@ chip soc/intel/alderlake
register "CpuPcieRpEnable[2]" = "1"
register "PcieClkSrcUsage[4]" = "0x42"
+ # W/A to FSP issue where FSP is using PCH PCIE port
+ # enable UPD to download FW on CPU PCIE
+ register "PchPcieRpEnable[0]" = "1"
+ register "PchPcieRpEnable[2]" = "1"
+ register "PchPcieRpEnable[3]" = "1"
+
# Mark LAN CLK pins as unused as GbE 0:0x1f.6 is disabled below
register "PcieClkSrcUsage[7]" = "PCIE_CLK_NOTUSED"
@@ -253,8 +259,8 @@ chip soc/intel/alderlake
device pci 19.2 off end # UART2
device pci 1c.0 on end # RP1
device pci 1c.1 off end # RP2
- device pci 1c.2 off end # RP3
- device pci 1c.3 off end # RP4
+ device pci 1c.2 on end # RP3 # W/A to FSP issue
+ device pci 1c.3 on end # RP4 # W/A to FSP issue
device pci 1c.4 on end # RP5
device pci 1c.5 on end # RP6
device pci 1c.6 off end # RP7