diff options
| author | Subrata Banik <subrata.banik@intel.com> | 2020-11-27 00:46:18 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2020-12-01 07:52:26 +0000 |
| commit | 840679d2c1d2d17e10866ae412332bb1a8a417b7 (patch) | |
| tree | b9c57ffcba9b81eb2d7a09af365e379e88aef47c /src/mainboard/intel | |
| parent | 0f044a50074d50dea18a73ffd2683b3860c205e2 (diff) | |
mainboard/intel/adlrvp: Enable PCH PCIe device over x1 slot
List of changes:
1. Enable Root Port 8 aka 0:0x1c:7
2. Assign free running clock for RP8
3. Apply W/A to get card detected on x1 slot
- Drive OEB 7:GPP_A7 and OEB 6:GPP_E5 low
TEST=Able to detect PCIe SD card over x1 slot
localhost ~ # dmesg | grep mmc
[ 3.643755] mmc0: SDHCI controller on PCI [0000:02:00.0] using ADMA
[ 3.825201] mmc0: new ultra high speed DDR50 SDHC card at address 17f8
[ 3.835452] mmcblk0: mmc0:17f8 SE16G 14.4 GiB
[ 3.849158] mmcblk0: p1
Change-Id: Ibea37b8de4dd020ff0108ec90ea6f8bcfaa4fb17
Signed-off-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/48080
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/adlrvp/devicetree.cb | 8 | ||||
| -rw-r--r-- | src/mainboard/intel/adlrvp/gpio.c | 4 |
2 files changed, 11 insertions, 1 deletions
diff --git a/src/mainboard/intel/adlrvp/devicetree.cb b/src/mainboard/intel/adlrvp/devicetree.cb index 80edb92003..f2f768a8be 100644 --- a/src/mainboard/intel/adlrvp/devicetree.cb +++ b/src/mainboard/intel/adlrvp/devicetree.cb @@ -51,6 +51,12 @@ chip soc/intel/alderlake register "PcieClkSrcUsage[5]" = "0x5" register "PcieRpClkReqDetect[5]" = "1" + # Enable PCH PCIE RP 8 using free running CLK (0x80) + register "PcieRpEnable[7]" = "1" + register "PcieClkSrcClkReq[7]" = "7" + register "PcieClkSrcUsage[7]" = "0x80" + register "PcieRpClkReqDetect[7]" = "1" + # Enable PCH PCIE RP 9 using CLK 1 register "PcieRpEnable[8]" = "1" register "PcieClkSrcClkReq[1]" = "1" @@ -245,7 +251,7 @@ chip soc/intel/alderlake device pci 1c.4 on end # RP5 device pci 1c.5 on end # RP6 device pci 1c.6 off end # RP7 - device pci 1c.7 off end # RP8 + device pci 1c.7 on end # RP8 device pci 1d.0 on end # RP9 device pci 1d.1 off end # RP10 device pci 1d.2 on end # RP11 diff --git a/src/mainboard/intel/adlrvp/gpio.c b/src/mainboard/intel/adlrvp/gpio.c index 89e6f5826b..4cb8c3a06c 100644 --- a/src/mainboard/intel/adlrvp/gpio.c +++ b/src/mainboard/intel/adlrvp/gpio.c @@ -72,6 +72,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_B4, 1, PLTRST), /* M.2_PCH_SSD_PWREN */ PAD_CFG_GPO(GPP_D16, 1, PLTRST), + /* SRCCLK_OEB7 */ + PAD_CFG_GPO(GPP_A7, 0, PLTRST), + /* SRCCLK_OEB6 */ + PAD_CFG_GPO(GPP_E5, 0, PLTRST), /* M.2_SSD_PDET_R */ PAD_CFG_NF(GPP_A12, NONE, DEEP, NF1), |