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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-06-16 23:29:23 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-06-21 09:00:57 +0000 |
| commit | 6beaef983aee5d886f6f8571855a92d608d98a17 (patch) | |
| tree | 9c7f858bc7baa36d9e18ed84ea61d742559922c2 /src/mainboard/intel | |
| parent | 4821a0e135ff2d60f552203d2724ae2d44850623 (diff) | |
sb/intel/bd82x6x: Set up io_gen_dec in romstage based on devicetree
Set up generic decode ranges based on the devicetree settings.
Change-Id: Ie59b8272c69231d6dffccee30b4d3c84a7e83e8f
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/33548
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: Patrick Rudolph <siro@das-labor.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/devicetree.cb | 5 | ||||
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/romstage.c | 6 |
2 files changed, 4 insertions, 7 deletions
diff --git a/src/mainboard/intel/emeraldlake2/devicetree.cb b/src/mainboard/intel/emeraldlake2/devicetree.cb index 60072b0995..4ed1f3c694 100644 --- a/src/mainboard/intel/emeraldlake2/devicetree.cb +++ b/src/mainboard/intel/emeraldlake2/devicetree.cb @@ -44,8 +44,11 @@ chip northbridge/intel/sandybridge register "sata_port_map" = "0x3f" + register "gen1_dec" = "0x00fc1601" + # runtime_port registers + register "gen2_dec" = "0x000c0181" # SuperIO range is 0x700-0x73f - register "gen2_dec" = "0x003c0701" + register "gen3_dec" = "0x003c0701" register "c2_latency" = "1" register "p_cnt_throttling_supported" = "0" diff --git a/src/mainboard/intel/emeraldlake2/romstage.c b/src/mainboard/intel/emeraldlake2/romstage.c index 9a9fc24677..a28ae78f28 100644 --- a/src/mainboard/intel/emeraldlake2/romstage.c +++ b/src/mainboard/intel/emeraldlake2/romstage.c @@ -39,12 +39,6 @@ void pch_enable_lpc(void) u16 lpc_config = CNF1_LPC_EN | CNF2_LPC_EN | KBC_LPC_EN; pci_write_config16(dev, LPC_EN, lpc_config); - /* Map 256 bytes at 0x1600 to the LPC bus. */ - pci_write_config32(dev, LPC_GEN1_DEC, 0xfc1601); - - /* Map a range for the runtime_port registers to the LPC bus. */ - pci_write_config32(dev, LPC_GEN2_DEC, 0xc0181); - /* Enable COM1 */ if (sio1007_enable_uart_at(SIO_PORT)) { pci_write_config16(dev, LPC_EN, |