mb/intel/tglrvp: Add initial mainboard code

This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Tigerlake".
 2. Replace "icelake_rvp" with "tglrvp".
 3. Rename "icl" with "tgl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add board support namely BOARD_INTEL_TGLRVP_UP3
 10. Replace icl_u and icl_y variant with tglrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per tigerlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 32MB BIOS region.
 5. clean up and make empty devicetree setting

TEST=Build tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

23 files changed, 961 insertions, 0 deletions

diff --git a/src/mainboard/intel/tglrvp/Kconfig b/src/mainboard/intel/tglrvp/Kconfig
new file mode 100644
index 0000000000..bee72cfdbe
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/Kconfig
@@ -0,0 +1,54 @@
+if BOARD_INTEL_TGLRVP_UP3
+
+config BOARD_SPECIFIC_OPTIONS
+	def_bool y
+	select BOARD_ROMSIZE_KB_32768
+	select EC_ACPI
+	select GENERIC_SPD_BIN
+	select HAVE_ACPI_RESUME
+	select HAVE_ACPI_TABLES
+	select MAINBOARD_HAS_CHROMEOS
+	select GENERIC_SPD_BIN
+	select DRIVERS_I2C_HID
+	select DRIVERS_I2C_GENERIC
+	select DRIVERS_USB_ACPI
+	select SOC_INTEL_TIGERLAKE
+	select MAINBOARD_USES_IFD_EC_REGION
+	select INTEL_LPSS_UART_FOR_CONSOLE
+
+config MAINBOARD_DIR
+	string
+	default "intel/tglrvp"
+
+config VARIANT_DIR
+	string
+	default "tglrvp_up3" if BOARD_INTEL_TGLRVP_UP3
+
+config MAINBOARD_PART_NUMBER
+	string
+	default "tglrvp"
+
+config MAINBOARD_FAMILY
+	string
+	default "Intel_tglrvp"
+
+config MAX_CPUS
+	int
+	default 8
+
+config DEVICETREE
+	string
+	default "variants/$(CONFIG_VARIANT_DIR)/devicetree.cb"
+
+config DIMM_SPD_SIZE
+	int
+	default 512
+
+config VBOOT
+	select VBOOT_LID_SWITCH
+	select VBOOT_MOCK_SECDATA
+
+config UART_FOR_CONSOLE
+	int
+	default 2
+endif
diff --git a/src/mainboard/intel/tglrvp/Kconfig.name b/src/mainboard/intel/tglrvp/Kconfig.name
new file mode 100644
index 0000000000..a2271f33cc
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/Kconfig.name
@@ -0,0 +1,2 @@
+config BOARD_INTEL_TGLRVP_UP3
+	bool "Tigerlake UP3 DDR4/LPDDR4 RVP"
diff --git a/src/mainboard/intel/tglrvp/Makefile.inc b/src/mainboard/intel/tglrvp/Makefile.inc
new file mode 100644
index 0000000000..81cbc6ee3a
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/Makefile.inc
@@ -0,0 +1,35 @@
+##
+## This file is part of the coreboot project.
+##
+##  Copyright (C) 2019 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+subdirs-y += spd
+
+bootblock-y += bootblock.c
+bootblock-$(CONFIG_CHROMEOS) += chromeos.c
+
+verstage-$(CONFIG_CHROMEOS) += chromeos.c
+
+romstage-$(CONFIG_CHROMEOS) += chromeos.c
+romstage-y += romstage_fsp_params.c
+romstage-y += board_id.c
+
+ramstage-$(CONFIG_CHROMEOS) += chromeos.c
+ramstage-y += mainboard.c
+ramstage-y += board_id.c
+
+subdirs-y += ../common
+subdirs-y += variants/baseboard
+CPPFLAGS_common += -I$(src)/mainboard/$(MAINBOARDDIR)/variants/baseboard/include
+
+subdirs-y += variants/$(VARIANT_DIR)
diff --git a/src/mainboard/intel/tglrvp/acpi/mainboard.asl b/src/mainboard/intel/tglrvp/acpi/mainboard.asl
new file mode 100644
index 0000000000..6647ac183f
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/acpi/mainboard.asl
@@ -0,0 +1,24 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+Scope (\_SB)
+{
+	Device (PWRB)
+	{
+		Name (_HID, EisaId ("PNP0C0C"))
+	}
+}
+#endif
diff --git a/src/mainboard/intel/tglrvp/board_id.c b/src/mainboard/intel/tglrvp/board_id.c
new file mode 100644
index 0000000000..23312565b1
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/board_id.c
@@ -0,0 +1,52 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <boardid.h>
+#include <ec/acpi/ec.h>
+#include <ec/google/chromeec/ec.h>
+#include <stdint.h>
+
+#include "board_id.h"
+
+static uint32_t get_board_id_via_ext_ec(void)
+{
+	uint32_t id = BOARD_ID_INIT;
+
+	if (google_chromeec_get_board_version(&id))
+		id = BOARD_ID_UNKNOWN;
+
+	return id;
+}
+
+/* Get Board ID via EC I/O port write/read */
+int get_board_id(void)
+{
+	MAYBE_STATIC_NONZERO int id = -1;
+
+	if (id < 0) {
+		if (CONFIG(EC_GOOGLE_CHROMEEC)) {
+			id = get_board_id_via_ext_ec();
+		} else {
+			uint8_t buffer[2];
+			uint8_t index;
+			if (send_ec_command(EC_FAB_ID_CMD) == 0) {
+				for (index = 0; index < sizeof(buffer); index++)
+					buffer[index] = recv_ec_data();
+				id = (buffer[0] << 8) | buffer[1];
+			}
+		}
+	}
+	return id;
+}
diff --git a/src/mainboard/intel/tglrvp/board_id.h b/src/mainboard/intel/tglrvp/board_id.h
new file mode 100644
index 0000000000..9aac527ad0
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/board_id.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef _MAINBOARD_COMMON_BOARD_ID_H_
+#define _MAINBOARD_COMMON_BOARD_ID_H_
+
+#include <stdint.h>
+
+/* Board/FAB ID Command */
+#define EC_FAB_ID_CMD	0x0D
+
+/*
+ * Returns board information (board id[15:8] and
+ * Fab info[7:0]) on success and < 0 on error
+ */
+int get_board_id(void);
+
+#endif /* _MAINBOARD_COMMON_BOARD_ID_H_ */
diff --git a/src/mainboard/intel/tglrvp/board_info.txt b/src/mainboard/intel/tglrvp/board_info.txt
new file mode 100644
index 0000000000..cecc5b4afe
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/board_info.txt
@@ -0,0 +1,6 @@
+Vendor name: Intel
+Board name: Tigerlake rvp
+Category: eval
+ROM protocol: SPI
+ROM socketed: n
+Flashrom support: y
diff --git a/src/mainboard/intel/tglrvp/bootblock.c b/src/mainboard/intel/tglrvp/bootblock.c
new file mode 100644
index 0000000000..01b257cf9e
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/bootblock.c
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <bootblock_common.h>
+#include <soc/gpio.h>
+
+void bootblock_mainboard_init(void)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_early_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
diff --git a/src/mainboard/intel/tglrvp/chromeos.c b/src/mainboard/intel/tglrvp/chromeos.c
new file mode 100644
index 0000000000..372f6cefa2
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/chromeos.c
@@ -0,0 +1,57 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <boot/coreboot_tables.h>
+#include <gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+void fill_lb_gpios(struct lb_gpios *gpios)
+{
+	struct lb_gpio chromeos_gpios[] = {
+		{-1, ACTIVE_HIGH, get_write_protect_state(), "write protect"},
+		{-1, ACTIVE_HIGH, get_lid_switch(), "lid"},
+		{-1, ACTIVE_HIGH, 0, "power"},
+		{-1, ACTIVE_HIGH, gfx_get_init_done(), "oprom"},
+	};
+	lb_add_gpios(gpios, chromeos_gpios, ARRAY_SIZE(chromeos_gpios));
+}
+
+int get_lid_switch(void)
+{
+	/* Lid always open */
+	return 1;
+}
+
+int get_recovery_mode_switch(void)
+{
+	return 0;
+}
+
+int get_write_protect_state(void)
+{
+	/* No write protect */
+	return 0;
+}
+
+void mainboard_chromeos_acpi_generate(void)
+{
+	const struct cros_gpio *gpios;
+	size_t num;
+
+	gpios = variant_cros_gpios(&num);
+	chromeos_acpi_gpio_generate(gpios, num);
+}
diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd
new file mode 100644
index 0000000000..bfbd304d36
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/chromeos.fmd
@@ -0,0 +1,44 @@
+FLASH@0xfe000000 0x2000000 {
+	SI_ALL@0x0 0x1081000 {
+		SI_DESC@0x0 0x1000
+		SI_EC@0x1000 0x80000
+		SI_ME@0x81000 0x1000000
+	}
+	SI_BIOS@0x1400000 0xC00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD@0x28000 0x2000
+			RW_NVRAM@0x2a000 0x6000
+		}
+		SMMSTORE@0x5d0000 0x40000
+		RW_LEGACY(CBFS)@0x610000 0x1c0000
+		WP_RO@0x7d0000 0x430000 {
+			RO_VPD@0x0 0x4000
+			RO_SECTION@0x4000 0x42c000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x33c000
+			}
+		}
+	}
+}
diff --git a/src/mainboard/intel/tglrvp/dsdt.asl b/src/mainboard/intel/tglrvp/dsdt.asl
new file mode 100644
index 0000000000..559e1e36cf
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/dsdt.asl
@@ -0,0 +1,68 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/acpi.h>
+#include <baseboard/ec.h>
+#include <baseboard/gpio.h>
+
+DefinitionBlock(
+	"dsdt.aml",
+	"DSDT",
+	0x02,		/* DSDT revision: ACPI v2.0 and up */
+	OEM_ID,
+	ACPI_TABLE_CREATOR,
+	0x20110725	/* OEM revision */
+)
+{
+	/* Some generic macros */
+	#include <soc/intel/tigerlake/acpi/platform.asl>
+
+	/* global NVS and variables */
+	#include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+
+	/* CPU */
+	#include <cpu/intel/common/acpi/cpu.asl>
+
+	Scope (\_SB) {
+		Device (PCI0)
+		{
+			#include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+			#include <soc/intel/tigerlake/acpi/southbridge.asl>
+		}
+	}
+
+#if CONFIG(CHROMEOS)
+	/* Chrome OS specific */
+	#include <vendorcode/google/chromeos/acpi/chromeos.asl>
+#endif
+
+#if CONFIG(EC_GOOGLE_CHROMEEC)
+	/* Chrome OS Embedded Controller */
+		Scope (\_SB.PCI0.LPCB)
+		{
+			/* ACPI code for EC SuperIO functions */
+			#include <ec/google/chromeec/acpi/superio.asl>
+			/* ACPI code for EC functions */
+			#include <ec/google/chromeec/acpi/ec.asl>
+		}
+#endif
+
+	/* Chipset specific sleep states */
+	#include <southbridge/intel/common/acpi/sleepstates.asl>
+
+	/* Mainboard specific */
+	#include "acpi/mainboard.asl"
+
+}
diff --git a/src/mainboard/intel/tglrvp/mainboard.c b/src/mainboard/intel/tglrvp/mainboard.c
new file mode 100644
index 0000000000..d74c11c8ca
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/mainboard.c
@@ -0,0 +1,39 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <device/device.h>
+#include <soc/gpio.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+static void mainboard_init(void *chip_info)
+{
+	const struct pad_config *pads;
+	size_t num;
+
+	pads = variant_gpio_table(&num);
+	gpio_configure_pads(pads, num);
+}
+
+static void mainboard_enable(struct device *dev)
+{
+	dev->ops->acpi_inject_dsdt_generator = chromeos_dsdt_generator;
+}
+
+struct chip_operations mainboard_ops = {
+	.init = mainboard_init,
+	.enable_dev = mainboard_enable,
+};
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
new file mode 100644
index 0000000000..0ab1f48fee
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -0,0 +1,22 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <fsp/api.h>
+#include <soc/romstage.h>
+
+void mainboard_memory_init_params(FSPM_UPD *mupd)
+{
+	/* ToDo : Fill FSP-M memory params */
+}
diff --git a/src/mainboard/intel/tglrvp/spd/Makefile.inc b/src/mainboard/intel/tglrvp/spd/Makefile.inc
new file mode 100644
index 0000000000..b8b059a1b7
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/Makefile.inc
@@ -0,0 +1,20 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+romstage-y += spd_util.c
+
+SPD_BIN = $(obj)/spd.bin
+
+SPD_SOURCES = empty	# 0b000
diff --git a/src/mainboard/intel/tglrvp/spd/empty.spd.hex b/src/mainboard/intel/tglrvp/spd/empty.spd.hex
new file mode 100644
index 0000000000..67b46cd239
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/empty.spd.hex
@@ -0,0 +1,32 @@
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 80 00 00 00 00 00 00 00 00 00 00 00 00 00 00
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+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
+00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00
diff --git a/src/mainboard/intel/tglrvp/spd/spd.h b/src/mainboard/intel/tglrvp/spd/spd.h
new file mode 100644
index 0000000000..ed8b8b6e0d
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/spd.h
@@ -0,0 +1,29 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef MAINBOARD_SPD_H
+#define MAINBOARD_SPD_H
+
+#include <stdint.h>
+
+#define RCOMP_TARGET_PARAMS	0x5
+
+void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr);
+void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr);
+void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr);
+void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr);
+void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr);
+void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr);
+#endif
diff --git a/src/mainboard/intel/tglrvp/spd/spd_util.c b/src/mainboard/intel/tglrvp/spd/spd_util.c
new file mode 100644
index 0000000000..4bfd964e30
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/spd/spd_util.c
@@ -0,0 +1,135 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <stdint.h>
+#include <string.h>
+
+#include "../board_id.h"
+#include "spd.h"
+
+enum tgl_dimm_type {
+	tgl_u_ddr4 = 0,
+	tgl_u_lpddr4 = 1,
+	tgl_u_lpddr4_type_3 = 4,
+	tgl_y_lpddr4 = 6
+};
+
+static uint8_t get_spd_index(void)
+{
+	uint8_t spd_index = (get_board_id() & 0x1F) & 0x7;
+
+	return spd_index;
+}
+
+void mainboard_fill_dq_map_ch0(u8 *dq_map_ptr)
+{
+	/* DQ byte map Ch0 */
+	const u8 dq_map[12] = {
+		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dq_map_ch1(u8 *dq_map_ptr)
+{
+	const u8 dq_map[12] = {
+		0x0F, 0xF0, 0x0F, 0xF0, 0xFF, 0x00,
+		0x00, 0x00, 0x00, 0x00, 0x00, 0x00 };
+
+	memcpy(dq_map_ptr, dq_map, sizeof(dq_map));
+}
+
+void mainboard_fill_dqs_map_ch0(u8 *dqs_map_ptr)
+{
+	/* DQS CPU<>DRAM map Ch0 */
+	const u8 dqs_map_u_ddr[8] = { 2, 0, 1, 3, 6, 4, 7, 5 };
+	const u8 dqs_map_u_lpddr[8] = { 2, 3, 0, 1, 7, 6, 4, 5 };
+	const u8 dqs_map_u_lpddr_type_3[8] = { 2, 3, 1, 0, 7, 6, 4, 5 };
+	const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 4, 5, 6, 7 };
+
+	switch (get_spd_index()) {
+	case tgl_u_ddr4:
+		memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
+		break;
+	case tgl_u_lpddr4:
+		memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
+		break;
+	case tgl_u_lpddr4_type_3:
+		memcpy(dqs_map_ptr, dqs_map_u_lpddr_type_3,
+				 sizeof(dqs_map_u_lpddr_type_3));
+		break;
+	case tgl_y_lpddr4:
+		memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
+		break;
+	default:
+		break;
+	}
+}
+
+void mainboard_fill_dqs_map_ch1(u8 *dqs_map_ptr)
+{
+	/* DQS CPU<>DRAM map Ch1 */
+	const u8 dqs_map_u_ddr[8] = { 1, 3, 2, 0, 5, 7, 6, 4 };
+	const u8 dqs_map_u_lpddr[8] = { 1, 0, 3, 2, 5, 4, 7, 6  };
+	const u8 dqs_map_y_lpddr[8] = { 0, 1, 2, 3, 5, 4, 7, 6 };
+
+	switch (get_spd_index()) {
+	case tgl_u_ddr4:
+		memcpy(dqs_map_ptr, dqs_map_u_ddr, sizeof(dqs_map_u_ddr));
+		break;
+	case tgl_u_lpddr4:
+	case tgl_u_lpddr4_type_3:
+		memcpy(dqs_map_ptr, dqs_map_u_lpddr, sizeof(dqs_map_u_lpddr));
+		break;
+	case tgl_y_lpddr4:
+		memcpy(dqs_map_ptr, dqs_map_y_lpddr, sizeof(dqs_map_y_lpddr));
+		break;
+	default:
+		break;
+	}
+}
+
+void mainboard_fill_rcomp_res_data(u16 *rcomp_ptr)
+{
+	/* Rcomp resistor */
+	const u16 RcompResistor[3] = { 100, 100, 100 };
+	memcpy(rcomp_ptr, RcompResistor, sizeof(RcompResistor));
+}
+
+void mainboard_fill_rcomp_strength_data(u16 *rcomp_strength_ptr)
+{
+	/* Rcomp target */
+	static const u16 RcompTarget_DDR4[RCOMP_TARGET_PARAMS] = {
+			100, 33, 32, 33, 28 };
+	static const u16 RcompTarget_LPDDR4_Ax[RCOMP_TARGET_PARAMS] = {
+			80, 40, 40, 40, 30 };
+
+	switch (get_spd_index()) {
+	case tgl_u_ddr4:
+		memcpy(rcomp_strength_ptr, RcompTarget_DDR4,
+				sizeof(RcompTarget_DDR4));
+		break;
+	case tgl_y_lpddr4:
+	case tgl_u_lpddr4:
+	case tgl_u_lpddr4_type_3:
+		memcpy(rcomp_strength_ptr, RcompTarget_LPDDR4_Ax,
+				sizeof(RcompTarget_LPDDR4_Ax));
+		break;
+	default:
+		break;
+	}
+}
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
new file mode 100644
index 0000000000..a8a147a3cd
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h
@@ -0,0 +1,80 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_EC_H__
+#define __BASEBOARD_EC_H__
+
+#include <ec/ec.h>
+#include <ec/google/chromeec/ec_commands.h>
+#include <baseboard/gpio.h>
+
+#define MAINBOARD_EC_SCI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED)        |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN)          |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_CONNECTED)      |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_AC_DISCONNECTED)   |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_LOW)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_CRITICAL)  |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY)           |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_STATUS)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_THRESHOLD) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_START)    |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_THROTTLE_STOP)     |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PD_MCU)            |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE)       |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MKBP))
+
+#define MAINBOARD_EC_SMI_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_CLOSED))
+
+/* EC can wake from S5 with lid or power button */
+#define MAINBOARD_EC_S5_WAKE_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_LID_OPEN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_POWER_BUTTON))
+
+/*
+ * EC can wake from S3 with lid or power button or key press or
+ * mode change event.
+ */
+#define MAINBOARD_EC_S3_WAKE_EVENTS \
+	(MAINBOARD_EC_S5_WAKE_EVENTS |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_KEY_PRESSED) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_MODE_CHANGE))
+
+/* Log EC wake events plus EC shutdown events */
+#define MAINBOARD_EC_LOG_EVENTS \
+	(EC_HOST_EVENT_MASK(EC_HOST_EVENT_THERMAL_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_BATTERY_SHUTDOWN) |\
+	 EC_HOST_EVENT_MASK(EC_HOST_EVENT_PANIC))
+
+/*
+ * ACPI related definitions for ASL code.
+ */
+
+/* Enable EC backed ALS device in ACPI */
+#define EC_ENABLE_ALS_DEVICE
+
+/* Enable EC backed PD MCU device in ACPI */
+#define EC_ENABLE_PD_MCU_DEVICE
+
+/* Enable LID switch and provide wake pin for EC */
+#define EC_ENABLE_LID_SWITCH
+#define EC_ENABLE_WAKE_PIN	GPE_EC_WAKE
+
+#define SIO_EC_MEMMAP_ENABLE	/* EC Memory Map Resources */
+#define SIO_EC_HOST_ENABLE	/* EC Host Interface Resources */
+#define SIO_EC_ENABLE_PS2K      /* Enable PS/2 Keyboard */
+
+#endif /* __BASEBOARD_EC_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
new file mode 100644
index 0000000000..227ec7563a
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h
@@ -0,0 +1,28 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_GPIO_H__
+#define __BASEBOARD_GPIO_H__
+
+#include <soc/gpe.h>
+#include <soc/gpio.h>
+
+/* eSPI virtual wire reporting */
+#define EC_SCI_GPI	GPE0_ESPI
+
+/* EC wake is LAN_WAKE# which is a special DeepSX wake pin */
+#define GPE_EC_WAKE	GPE0_LAN_WAK
+
+#endif /* __BASEBOARD_GPIO_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
new file mode 100644
index 0000000000..9220b1140c
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
@@ -0,0 +1,30 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#ifndef __BASEBOARD_VARIANTS_H__
+#define __BASEBOARD_VARIANTS_H__
+
+#include <soc/gpio.h>
+#include <stdint.h>
+#include <vendorcode/google/chromeos/chromeos.h>
+
+/* The next set of functions return the gpio table and fill in the number of
+ * entries for each table. */
+
+const struct pad_config *variant_gpio_table(size_t *num);
+const struct pad_config *variant_early_gpio_table(size_t *num);
+const struct cros_gpio *variant_cros_gpios(size_t *num);
+
+#endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
new file mode 100644
index 0000000000..23bf160883
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
@@ -0,0 +1,18 @@
+##
+## This file is part of the coreboot project.
+##
+## Copyright (C) 2019 Intel Corporation.
+##
+## This program is free software; you can redistribute it and/or modify
+## it under the terms of the GNU General Public License as published by
+## the Free Software Foundation; version 2 of the License.
+##
+## This program is distributed in the hope that it will be useful,
+## but WITHOUT ANY WARRANTY; without even the implied warranty of
+## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+## GNU General Public License for more details.
+##
+
+bootblock-y += gpio.c
+
+ramstage-y += gpio.c
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
new file mode 100644
index 0000000000..6a4bae894c
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -0,0 +1,78 @@
+chip soc/intel/tigerlake
+
+	device cpu_cluster 0 on
+		device lapic 0 on end
+	end
+
+
+	device domain 0 on
+		#From EDS(575683)
+		device pci 00.0 on  end # Host Bridge		0x9A14:U/0x9A12:Y
+		device pci 02.0 on  end # Graphics
+		device pci 04.0 on  end # DPTF			0x9A03
+		device pci 05.0 on  end # IPU			0x9A19
+		device pci 06.0 on  end # PEG60			0x9A09
+		device pci 07.0 off end # TBT_PCIe0		0x9A23
+		device pci 07.1 off end # TBT_PCIe1		0x9A25
+		device pci 07.2 off end # TBT_PCIe2		0x9A27
+		device pci 07.3 off end # TBT_PCIe3		0x9A29
+		device pci 08.0 off end # GNA			0x9A11
+		device pci 09.0 off end # NPK			0x9A33
+		device pci 0a.0 off end # Crash-log SRAM	0x9A0D
+		device pci 0d.0 on  end # USB xHCI		0x9A13
+		device pci 0d.1 on  end # USB xDCI (OTG)	0x9A15
+		device pci 0d.2 off end # TBT DMA0		0x9A1B
+		device pci 0d.3 off end # TBT DMA1		0x9A1D
+		device pci 0e.0 on  end # VMD			0x9A0B
+
+		# From PCH EDS(576591)
+		device pci 10.2 off end # CNVi: BT		0xA0F5 - A0F7
+		device pci 10.6 off end # THC0			0xA0D0
+		device pci 10.7 off end # THC1			0xA0D1
+		device pci 12.0 off end # SensorHUB		0xA0FC
+		device pci 12.6 off end # GSPI2			0x34FB
+		device pci 13.0 off end # GSPI3			0xA0FD
+		device pci 14.0 on  end # USB3.1 xHCI 		0xA0ED
+		device pci 14.1 on  end # USB3.1 xDCI		0xA0EE
+		device pci 14.2 on  end # Shared RAM		0xA0EF
+		device pci 14.3 off end # CNVi: WiFi		0xA0F0 - A0F3
+		device pci 15.0 on  end	# I2C0			0xA0E8
+		device pci 15.1 on  end # I2C1			0xA0E9
+		device pci 15.2 on  end # I2C2			0xA0EA
+		device pci 15.3 on  end # I2C3			0xA0EB
+		device pci 16.0 on  end # HECI1			0xA0E0
+		device pci 16.1 off end # HECI2			0xA0E1
+		device pci 16.2 off end # CSME			0xA0E2
+		device pci 16.3 off end # CSME			0xA0E3
+		device pci 16.4 off end # HECI3			0xA0E4
+		device pci 16.5 off end # HECI4			0xA0E5
+		device pci 17.0 off end # SATA			0xA0D3
+		device pci 19.0 off end # I2C4			0xA0C5
+		device pci 19.1 on  end # I2C5			0xA0C6
+		device pci 19.2 on  end # UART2			0xA0C7
+		device pci 1c.0 off end # RP1			0xA0B8
+		device pci 1c.1 off end # RP2			0xA0B9
+		device pci 1c.2 on  end # RP3			0xA0BA
+		device pci 1c.3 on  end # RP4			0xA0BB
+		device pci 1c.4 off end # RP5			0xA0BC
+		device pci 1c.5 off end # RP6			0xA0BD
+		device pci 1c.6 off end # RP7			0xA0BE
+		device pci 1c.7 off end # RP8			0xA0BF
+		device pci 1d.0 on  end # RP9			0xA0B0
+		device pci 1d.1 on  end # RP10			0xA0B1
+		device pci 1d.2 off end # RP11			0xA0B2
+		device pci 1d.3 off end # RP12			0xA0B3
+		device pci 1e.0 off end # UART0			0xA0A8
+		device pci 1e.1 off end # UART1			0xA0A9
+		device pci 1e.2 off end # GSPI0			0xA0AA
+		device pci 1e.3 off end # GSPI1			0xA0AB
+		device pci 1f.0 on  end # eSPI			0xA080 - A09F
+		device pci 1f.1 on  end # P2SB			0xA0A0
+		device pci 1f.2 on  end # PMC			0xA0A1
+		device pci 1f.3 on  end # Intel HD audio	0xA0C8-A0CF
+		device pci 1f.4 on  end # SMBus			0xA0A3
+		device pci 1f.5 on  end # SPI			0xA0A4
+		device pci 1f.6 off end # GbE			0x15E1/0x15E2
+		device pci 1f.7 off end # TH			0xA0A6
+	end
+end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
new file mode 100644
index 0000000000..48ad36edb2
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c
@@ -0,0 +1,50 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2019 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <baseboard/gpio.h>
+#include <baseboard/variants.h>
+#include <commonlib/helpers.h>
+
+/* Pad configuration in ramstage*/
+static const struct pad_config gpio_table[] = {
+	/* ToDo: Fill gpio configuration */
+};
+
+/* Early pad configuration in bootblock */
+static const struct pad_config early_gpio_table[] = {
+/* ToDo: Fill early gpio configurations for TPM and WWAN */
+};
+
+const struct pad_config *variant_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(gpio_table);
+	return gpio_table;
+}
+
+const struct pad_config *variant_early_gpio_table(size_t *num)
+{
+	*num = ARRAY_SIZE(early_gpio_table);
+	return early_gpio_table;
+}
+
+static const struct cros_gpio cros_gpios[] = {
+	CROS_GPIO_REC_AL(CROS_GPIO_VIRTUAL, CROS_GPIO_DEVICE_NAME),
+};
+
+const struct cros_gpio *variant_cros_gpios(size_t *num)
+{
+	*num = ARRAY_SIZE(cros_gpios);
+	return cros_gpios;
+}