mb/intel/adlrvp: Add support for LPDDR5

This patch adds LPDDR5 memory configuration parameters to FSP.

TEST=Able to pass FSP-M MRC training on LPDDR5 RVP.

Signed-off-by: Sridhar Siricilla <sridhar.siricilla@intel.com>
Change-Id: I787bf97dd6c244bd3b0662e5bd061a2da80baa90
Reviewed-on: https://review.coreboot.org/c/coreboot/+/46899
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-by: V Sowmya <v.sowmya@intel.com>

5 files changed, 71 insertions, 4 deletions

diff --git a/src/mainboard/intel/adlrvp/include/baseboard/variants.h b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
index 537e62451a..9cb8640860 100644
--- a/src/mainboard/intel/adlrvp/include/baseboard/variants.h
+++ b/src/mainboard/intel/adlrvp/include/baseboard/variants.h
@@ -14,6 +14,8 @@ enum adl_boardid {
 	ADL_P_LP4_2 = 0x11,
 	/* ADL-P DDR5 RVPs */
 	ADL_P_DDR5 = 0x12,
+	/* ADL-P LPDDR5 RVP */
+	ADL_P_LP5 = 0x13,
 	/* ADL-P DDR4 RVPs */
 	ADL_P_DDR4_1 = 0x14,
 	ADL_P_DDR4_2 = 0x3F,
diff --git a/src/mainboard/intel/adlrvp/memory.c b/src/mainboard/intel/adlrvp/memory.c
index b203f69240..80ec14aa17 100644
--- a/src/mainboard/intel/adlrvp/memory.c
+++ b/src/mainboard/intel/adlrvp/memory.c
@@ -44,6 +44,34 @@ static const struct mb_cfg lpddr4_mem_config = {
 	.UserBd = BOARD_TYPE_MOBILE,
 };
 
+static const struct mb_cfg lp5_mem_config = {
+
+	/* DQ byte map */
+	.dq_map = {
+		{  3,  2,  1,  0,  5,  4,  6,  7, 15, 14, 12, 13,  8,  9, 10, 11 },
+		{  0,  2,  3,  1,  5,  7,  4,  6, 14, 13, 15, 12,  8,  9, 11, 10 },
+		{  1,  2,  0,  3,  4,  6,  5,  7, 15, 13, 12, 14,  9, 10,  8, 11 },
+		{  2,  1,  3,  0,  7,  4,  5,  6, 13, 12, 15, 14,  9, 11,  8, 10 },
+		{  1,  2,  3,  0,  6,  4,  5,  7, 15, 13, 14, 12, 10,  9,  8, 11 },
+		{  1,  0,  3,  2,  6,  7,  4,  5, 14, 12, 15, 13,  8,  9, 10, 11 },
+		{  0,  2,  1,  3,  4,  7,  5,  6, 12, 13, 15, 14,  9, 11, 10,  8 },
+		{  3,  2,  1,  0,  5,  4,  6,  7, 13, 15, 11, 12, 10,  9, 14,  8 },
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+		{ 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }, { 0, 1 }
+	},
+
+	.dq_pins_interleaved = false,
+
+	.ect = false, /* Early Command Training */
+
+	.lp5_ccc_config = 0xff,
+
+	.UserBd = BOARD_TYPE_MOBILE,
+};
+
 static const struct mb_cfg ddr5_mem_config = {
 	/* Baseboard uses only 100ohm Rcomp resistors */
 	.rcomp_resistor = {100, 100, 100},
@@ -71,6 +99,8 @@ const struct mb_cfg *variant_memory_params(void)
 		return &ddr4_mem_config;
 	case ADL_P_DDR5:
 		return &ddr5_mem_config;
+	case ADL_P_LP5:
+		return &lp5_mem_config;
 	default:
 		die("unsupported board id : 0x%x\n", board_id);
 	}
diff --git a/src/mainboard/intel/adlrvp/romstage_fsp_params.c b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
index 672c59743e..2f03cb4e84 100644
--- a/src/mainboard/intel/adlrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/adlrvp/romstage_fsp_params.c
@@ -31,7 +31,7 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 	int board_id = get_board_id();
 	const bool half_populated = false;
 
-	const struct spd_info lpddr4_spd_info = {
+	const struct spd_info lp4_lp5_spd_info = {
 		.read_type = READ_SPD_CBFS,
 		.spd_spec.spd_index = get_spd_index(),
 	};
@@ -56,7 +56,8 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
 		break;
 	case ADL_P_LP4_1:
 	case ADL_P_LP4_2:
-		memcfg_init(&mupd->FspmConfig, mem_config, &lpddr4_spd_info, half_populated);
+	case ADL_P_LP5:
+		memcfg_init(&mupd->FspmConfig, mem_config, &lp4_lp5_spd_info, half_populated);
 		break;
 	default:
 		die("Unknown board id = 0x%x\n", board_id);
diff --git a/src/mainboard/intel/adlrvp/spd/Makefile.inc b/src/mainboard/intel/adlrvp/spd/Makefile.inc
index 1218a76690..10ce42ef4c 100644
--- a/src/mainboard/intel/adlrvp/spd/Makefile.inc
+++ b/src/mainboard/intel/adlrvp/spd/Makefile.inc
@@ -1,4 +1,6 @@
 ## SPDX-License-Identifier: GPL-2.0-only
 
-SPD_SOURCES = adlrvp_lp4 #0b000
-SPD_SOURCES += empty # 0b001
+SPD_SOURCES =  adlrvp_lp4 # 0b000
+SPD_SOURCES += empty      # 0b001
+SPD_SOURCES += empty      # 0b002
+SPD_SOURCES += adlrvp_lp5 # 0b003
diff --git a/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex
new file mode 100644
index 0000000000..2f2a31a33d
--- /dev/null
+++ b/src/mainboard/intel/adlrvp/spd/adlrvp_lp5.spd.hex
@@ -0,0 +1,32 @@
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