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authorKayalvizhi Dhandapani <kayalvizhid@ami.com>2014-10-07 14:34:01 -0400
committerMarc Jones <marc.jones@se-eng.com>2014-10-09 21:59:45 +0200
commit454625c5cf4adecb5b80777503bc600c8b139004 (patch)
tree753330c0244e6419ab51e8e6c374293e471203d5 /src/mainboard/intel
parent2c0f46afbbee078881ad9e9a99f5c219c2ed528e (diff)
intel/fsp_baytrail: Fix SMM/SMI
With SMM enabled the boot stopped while patching up global NVS in DSDT. The cause is that both CPUs are assigned the same SMBASE address. So update the "cpu_smm_do_relocation()" function so that each CPU gets a different SMBASE address Based on rmodule work that wasn't propagated to the FSP version: commit 3eb8eb7eba55cdfd64c8d50181ea066526ff6485 Change-Id: I77cd27d3a4f207411a689b5be572b4406a03f16b Signed-off-by: Kayalvizhi Dhandapani <kayalvizhid@ami.com> Reviewed-on: http://review.coreboot.org/7026 Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net> Reviewed-by: Marc Jones <marc.jones@se-eng.com> Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/bayleybay_fsp/devicetree.cb2
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/bayleybay_fsp/devicetree.cb b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
index befd3dce25..356c8df5f3 100644
--- a/src/mainboard/intel/bayleybay_fsp/devicetree.cb
+++ b/src/mainboard/intel/bayleybay_fsp/devicetree.cb
@@ -27,7 +27,7 @@ chip soc/intel/fsp_baytrail
register "SataMode" = "SATA_MODE_AHCI"
register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT"
register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT"
- register "MrcInitTsegSize" = "TSEG_SIZE_DEFAULT"
+ register "MrcInitTsegSize" = "TSEG_SIZE_8_MB"
register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT"
register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE"
register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT"