diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2020-02-24 13:26:04 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-02-26 17:06:40 +0000 |
| commit | 44f558ec262c671d4db76ae25eb1b8e24204d002 (patch) | |
| tree | f66b2fe59486b6bcdb094822f9b57b4d09537b90 /src/mainboard/intel | |
| parent | dfd3f211740be4cf0d234bf4621ac384758a24ce (diff) | |
treewide: capitalize 'USB'
Change-Id: I7650786ea50465a4c2d11de948fdb81f4e509772
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39100
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/emeraldlake2/early_init.c | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/harcuvar/hsio.h | 10 |
2 files changed, 6 insertions, 6 deletions
diff --git a/src/mainboard/intel/emeraldlake2/early_init.c b/src/mainboard/intel/emeraldlake2/early_init.c index 2d97c8599c..0bc5884e6a 100644 --- a/src/mainboard/intel/emeraldlake2/early_init.c +++ b/src/mainboard/intel/emeraldlake2/early_init.c @@ -111,7 +111,7 @@ void mainboard_fill_pei_data(struct pei_data *pei_data) } const struct southbridge_usb_port mainboard_usb_ports[] = { - /* enabled power usb oc pin */ + /* enabled power USB oc pin */ { 1, 0, 0 }, /* P0: Front port (OC0) */ { 1, 0, 1 }, /* P1: Back port (OC1) */ { 1, 0, -1 }, /* P2: MINIPCIE1 (no OC) */ diff --git a/src/mainboard/intel/harcuvar/hsio.h b/src/mainboard/intel/harcuvar/hsio.h index ce059fd8fd..c59cfd02f8 100644 --- a/src/mainboard/intel/harcuvar/hsio.h +++ b/src/mainboard/intel/harcuvar/hsio.h @@ -38,7 +38,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { * Lane[19]->USB3 rear I/O panel connector */ - /* SKU HSIO 20 (pcie [0-15] sata [16-18] usb [19]) */ + /* SKU HSIO 20 (pcie [0-15] sata [16-18] USB [19]) */ {BL_SKU_HSIO_20, {PCIE_BIF_CTRL_x8, PCIE_BIF_CTRL_x4x4}, {/* ME_FIA_MUX_CONFIG */ @@ -155,7 +155,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] usb [19]) */ + /* SKU HSIO 12 (pcie [0-3, 8-9, 12-13] sata [16-18] USB [19]) */ {BL_SKU_HSIO_12, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/*ME_FIA_MUX_CONFIG */ @@ -272,7 +272,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 10 (pcie [0-3, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_10, {PCIE_BIF_CTRL_x4x4, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -388,7 +388,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] usb [19]) */ + /* SKU HSIO 8 (pcie [0-1, 8-9, 12] sata [16-17] USB [19]) */ {BL_SKU_HSIO_08, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ @@ -504,7 +504,7 @@ const BL_HSIO_INFORMATION harcuvar_hsio_config[] = { BL_ME_FIA_PCIE_ROOT_PORT_LINK_WIDTH_BICTRL, BL_FIA_PCIE_ROOT_PORT_7)} } }, - /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] usb [19]) */ + /* SKU HSIO 6 (pcie [0-1, 8, 12] sata [16] USB [19]) */ {BL_SKU_HSIO_06, {PCIE_BIF_CTRL_x2x2x2x2, PCIE_BIF_CTRL_x2x2x2x2}, {/* ME_FIA_MUX_CONFIG */ |