diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2020-07-03 13:43:19 +0200 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2020-07-08 22:27:01 +0000 |
| commit | 279ace666991855330b10d965a6a497f1a018432 (patch) | |
| tree | 16836faa64311d426a608e79fff62088bff2b72a /src/mainboard/intel | |
| parent | 725657aa4c8fa97b0daad18a759d9263029a28bf (diff) | |
mb/intel/baskingridge: Put GPIOs in a C file
This will allow dropping the pointer inside romstage_params.
Change-Id: I04b695cbe2a6485b42ab037f4f7359a2429c3440
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/43100
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tristan Corrick <tristan@corrick.kiwi>
Diffstat (limited to 'src/mainboard/intel')
| -rw-r--r-- | src/mainboard/intel/baskingridge/Makefile.inc | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/baskingridge/gpio.c (renamed from src/mainboard/intel/baskingridge/gpio.h) | 5 | ||||
| -rw-r--r-- | src/mainboard/intel/baskingridge/romstage.c | 2 |
3 files changed, 3 insertions, 6 deletions
diff --git a/src/mainboard/intel/baskingridge/Makefile.inc b/src/mainboard/intel/baskingridge/Makefile.inc index f157ec005d..46c9af28b7 100644 --- a/src/mainboard/intel/baskingridge/Makefile.inc +++ b/src/mainboard/intel/baskingridge/Makefile.inc @@ -1,5 +1,7 @@ ## SPDX-License-Identifier: GPL-2.0-only +romstage-y += gpio.c + romstage-y += chromeos.c ramstage-y += chromeos.c verstage-$(CONFIG_VBOOT_SEPARATE_VERSTAGE) += chromeos.c diff --git a/src/mainboard/intel/baskingridge/gpio.h b/src/mainboard/intel/baskingridge/gpio.c index bb37d56c6b..6c9235a035 100644 --- a/src/mainboard/intel/baskingridge/gpio.h +++ b/src/mainboard/intel/baskingridge/gpio.c @@ -1,8 +1,5 @@ /* SPDX-License-Identifier: GPL-2.0-only */ -#ifndef BASKING_RIDGE_GPIO_H -#define BASKING_RIDGE_GPIO_H - #include <southbridge/intel/common/gpio.h> const struct pch_gpio_set1 pch_gpio_set1_mode = { @@ -226,5 +223,3 @@ const struct pch_gpio_map mainboard_gpio_map = { .level = &pch_gpio_set3_level, }, }; - -#endif diff --git a/src/mainboard/intel/baskingridge/romstage.c b/src/mainboard/intel/baskingridge/romstage.c index a71d0bd078..50499eaa19 100644 --- a/src/mainboard/intel/baskingridge/romstage.c +++ b/src/mainboard/intel/baskingridge/romstage.c @@ -7,7 +7,7 @@ #include <northbridge/intel/haswell/haswell.h> #include <northbridge/intel/haswell/raminit.h> #include <southbridge/intel/lynxpoint/pch.h> -#include "gpio.h" +#include <southbridge/intel/common/gpio.h> const struct rcba_config_instruction rcba_config[] = { /* |