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authorKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-14 18:51:34 +0300
committerKyösti Mälkki <kyosti.malkki@gmail.com>2014-06-20 19:50:50 +0200
commit12d681b23f4c1e24cb31f5f253ec42290ca9c5ee (patch)
tree58599b05bceab19e77aa4766c80fced4fe745ade /src/mainboard/intel
parent2ca2afe760bf1f78ee410749332d85f9413a9f3a (diff)
intel/i945 gm45: Use acpi_s3_resume_allowed()
Change-Id: I7811ee695f35c708144c4af5d43935deb22dd4df Signed-off-by: Kyösti Mälkki <kyosti.malkki@gmail.com> Reviewed-on: http://review.coreboot.org/6061 Tested-by: build bot (Jenkins) Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com> Reviewed-by: Marc Jones <marc.jones@se-eng.com>
Diffstat (limited to 'src/mainboard/intel')
-rw-r--r--src/mainboard/intel/d945gclf/romstage.c21
1 files changed, 11 insertions, 10 deletions
diff --git a/src/mainboard/intel/d945gclf/romstage.c b/src/mainboard/intel/d945gclf/romstage.c
index 69d4232edd..1ae632debc 100644
--- a/src/mainboard/intel/d945gclf/romstage.c
+++ b/src/mainboard/intel/d945gclf/romstage.c
@@ -26,6 +26,7 @@
#include <device/pnp_def.h>
#include <cpu/x86/lapic.h>
#include <lib.h>
+#include <arch/acpi.h>
#include <cbmem.h>
#include "superio/smsc/lpc47m15x/lpc47m15x.h"
#include <pc80/mc146818rtc.h>
@@ -215,16 +216,16 @@ void main(unsigned long bist)
reg32 = inl(DEFAULT_PMBASE + 0x04);
printk(BIOS_DEBUG, "PM1_CNT: %08x\n", reg32);
if (((reg32 >> 10) & 7) == 5) {
-#if CONFIG_HAVE_ACPI_RESUME
- printk(BIOS_DEBUG, "Resume from S3 detected.\n");
- boot_mode = 2;
- /* Clear SLP_TYPE. This will break stage2 but
- * we care for that when we get there.
- */
- outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
-#else
- printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
-#endif
+ if (acpi_s3_resume_allowed()) {
+ printk(BIOS_DEBUG, "Resume from S3 detected.\n");
+ boot_mode = 2;
+ /* Clear SLP_TYPE. This will break stage2 but
+ * we care for that when we get there.
+ */
+ outl(reg32 & ~(7 << 10), DEFAULT_PMBASE + 0x04);
+ } else {
+ printk(BIOS_DEBUG, "Resume from S3 detected, but disabled.\n");
+ }
}
/* Enable SPD ROMs and DDR-II DRAM */