Since some people disapprove of white space cleanups mixed in regular commits

while others dislike them being extra commits, let's clean them up once and
for all for the existing code. If it's ugly, let it only be ugly once :-)

Signed-off-by: Stefan Reinauer <stepan@coresystems.de>
Acked-by: Stefan Reinauer <stepan@coresystems.de>



git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5507 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1

6 files changed, 28 insertions, 28 deletions

diff --git a/src/mainboard/intel/xe7501devkit/acpi_tables.c b/src/mainboard/intel/xe7501devkit/acpi_tables.c
index fd43eb693b..1188467f20 100644
--- a/src/mainboard/intel/xe7501devkit/acpi_tables.c
+++ b/src/mainboard/intel/xe7501devkit/acpi_tables.c
@@ -38,21 +38,21 @@ unsigned long acpi_fill_madt(unsigned long current)
 	device_t dev = 0;
     struct resource* res = NULL;
 
- 
+
 	// SJM: Hard-code CPU LAPIC entries for now
 	//		Use SourcePoint numbering of processors
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 0, 6);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 1, 7);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 2, 0);
 	current += acpi_create_madt_lapic((acpi_madt_lapic_t *)current, 3, 1);
-	
+
 
 	// Southbridge IOAPIC
 	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *)current, IOAPIC_ICH3, 0xfec00000, irq_start);
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -60,7 +60,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -69,7 +69,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 
 
 	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -77,7 +77,7 @@ unsigned long acpi_fill_madt(unsigned long current)
 	irq_start += INTEL_IOAPIC_NUM_INTERRUPTS;
 
 	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -104,7 +104,7 @@ unsigned long write_acpi_tables(unsigned long start)
 	/* Align ACPI tables to 16byte */
 	start   = ( start + 0x0f ) & -0x10;
 	current = start;
-	
+
 	printk(BIOS_INFO, "ACPI: Writing ACPI tables at %lx...\n", start);
 
 	/* We need at least an RSDP and an RSDT Table */
@@ -115,10 +115,10 @@ unsigned long write_acpi_tables(unsigned long start)
 
 	/* clear all table memory */
 	memset((void *)start, 0, current - start);
-	
+
 	acpi_write_rsdp(rsdp, rsdt, NULL);
 	acpi_write_rsdt(rsdt);
-	
+
 	/*
 	 * We explicitly add these tables later on:
 	 */
diff --git a/src/mainboard/intel/xe7501devkit/cmos.layout b/src/mainboard/intel/xe7501devkit/cmos.layout
index 494af5bb61..baae5eb617 100644
--- a/src/mainboard/intel/xe7501devkit/cmos.layout
+++ b/src/mainboard/intel/xe7501devkit/cmos.layout
@@ -1,4 +1,4 @@
-# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails: 
+# NOTE: This file must be in UNIX format (not DOS) or build_opt_tbl fails:
 # "Error - Name  is an invalid identifier in line"
 
 entries
diff --git a/src/mainboard/intel/xe7501devkit/ioapic.h b/src/mainboard/intel/xe7501devkit/ioapic.h
index 30ae8e7a73..9ac2aee3f8 100644
--- a/src/mainboard/intel/xe7501devkit/ioapic.h
+++ b/src/mainboard/intel/xe7501devkit/ioapic.h
@@ -1,6 +1,6 @@
-// IOAPIC addresses determined by coreboot enumeration. 
+// IOAPIC addresses determined by coreboot enumeration.
 // Someday add functions to get APIC IDs and versions from the chips themselves.
-	
+
 #define IOAPIC_ICH3				2
 #define IOAPIC_P64H2_2_BUS_B	3	// IOAPIC 3 at 01:1c.0  MBAR = fe300000 DataAddr = fe300010
 #define IOAPIC_P64H2_2_BUS_A	4	// IOAPIC 4 at 01:1e.0  MBAR = fe301000 DataAddr = fe301010
diff --git a/src/mainboard/intel/xe7501devkit/irq_tables.c b/src/mainboard/intel/xe7501devkit/irq_tables.c
index b329351b6b..951b08f5f8 100644
--- a/src/mainboard/intel/xe7501devkit/irq_tables.c
+++ b/src/mainboard/intel/xe7501devkit/irq_tables.c
@@ -35,17 +35,17 @@ const struct irq_routing_table intel_irq_routing_table = {
 		// bitmap of 0xdcf8 == routable to IRQ3-IRQ7, IRQ10-IRQ12, or IRQ14-IRQ15
 		// ICH-3 doesn't allow SERIRQ or PCI message to generate IRQ0, IRQ2, IRQ8, or IRQ13
 		// Not sure why IRQ9 isn't routable (inherited from Tyan S2735)
-		
+
 		//											INTA#			   INTB#		     INTC#		      INTD#
 	//  bus,				device #  		   {link  , bitmap}, {link  , bitmap}, {link  , bitmap}, {link  , bitmap},  slot, rfu
-		
+
 		{PCI_BUS_CHIPSET,	PCI_DEVFN(31, 0), {{PIRQ_C, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// IDE / SMBus
 		{PCI_BUS_CHIPSET,	PCI_DEVFN(29, 0), {{PIRQ_A, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_C, 0xdcf8}, UNUSED_INTERRUPT},   0, 0},	// USB 1.1
-		
+
 		// P64H2#2 Bus A
 		{PCI_BUS_P64H2_2_A, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// SCSI
 			// NOTE: Hotplug disabled on this bus
-		
+
 		// P64H2#2 Bus B
 		{PCI_BUS_P64H2_2_B, PCI_DEVFN(1, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  23, 0},	// Slot 2A (J23)
 		{PCI_BUS_P64H2_2_B, PCI_DEVFN(2, 0),  {{PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}, {PIRQ_B, 0xdcf8}},  24, 0},	// Slot 2B (J24)
@@ -61,7 +61,7 @@ const struct irq_routing_table intel_irq_routing_table = {
 		{PCI_BUS_P64H2_1_B, PCI_DEVFN(1, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// GB Ethernet
 		{PCI_BUS_P64H2_1_B, PCI_DEVFN(2, 0),  {{PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_A, 0xdcf8}},  21, 0},	// Slot 1B (J21)
 			// NOTE: Hotplug disabled on this bus
-	
+
 		// ICH-3 PCI bus
 		{PCI_BUS_ICH3,		PCI_DEVFN(0, 0),  {{PIRQ_A, 0xdcf8}, UNUSED_INTERRUPT, UNUSED_INTERRUPT, UNUSED_INTERRUPT},   0, 0},	// Video
 		{PCI_BUS_ICH3,		PCI_DEVFN(2, 0),  {{PIRQ_C, 0xdcf8}, {PIRQ_D, 0xdcf8}, {PIRQ_A, 0xdcf8}, {PIRQ_B, 0xdcf8}},  11, 0},	// Debug slot (J11)
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c
index ee8299389d..2f48e83285 100644
--- a/src/mainboard/intel/xe7501devkit/mptable.c
+++ b/src/mainboard/intel/xe7501devkit/mptable.c
@@ -40,14 +40,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 	smp_write_ioapic(mc, IOAPIC_ICH3, 0x20, 0xfec00000);	// APIC ID, Version, Address
 
 	// P64H2#2 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_2_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#2 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_B, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -55,14 +55,14 @@ static void xe7501devkit_register_ioapics(struct mp_config_table *mc)
 
 
 	// P64H2#1 Bus A IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(30, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
 	smp_write_ioapic(mc, IOAPIC_P64H2_1_BUS_A, P64H2_IOAPIC_VERSION, res->base);
 
 	// P64H2#1 Bus B IOAPIC
-	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));	
+	dev = dev_find_slot(PCI_BUS_E7501_HI_D, PCI_DEVFN(28, 0));
 	if (!dev)
 		BUG();		// Config.lb error?
 	res = find_resource(dev, PCI_BASE_ADDRESS_0);
@@ -98,11 +98,11 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_B), 	IOAPIC_P64H2_2_BUS_B,   13);	// Slot 2D (J12)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_C), 	IOAPIC_P64H2_2_BUS_B,   14);	// Slot 2D (J12)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_2_B, 	PCI_IRQ(4, INT_D), 	IOAPIC_P64H2_2_BUS_B,   15);	// Slot 2D (J12)
-	
+
 	// P64H2#2 Bus A
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_A),	IOAPIC_P64H2_2_BUS_A,	 0);	// SCSI
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_P64H2_2_A, 	PCI_IRQ(1, INT_B),	IOAPIC_P64H2_2_BUS_A,	 1);	// SCSI
-	
+
 	// P64H2#1 Bus B
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(1, INT_A), 	IOAPIC_P64H2_1_BUS_B,    0);	// GB Ethernet
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_B, 	PCI_IRQ(2, INT_A), 	IOAPIC_P64H2_1_BUS_B,    4);	// Slot 1B (J21)
@@ -117,13 +117,13 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc)
 	smp_write_intsrc(mc, mp_INT, 	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, 	PCI_BUS_P64H2_1_A, 	PCI_IRQ(1, INT_D), 	IOAPIC_P64H2_1_BUS_A,    3);	// Slot 1A (J20)
 
 	// ICH-3
-	
+
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(0, INT_A),	IOAPIC_ICH3,			16);	// Video
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_A),	IOAPIC_ICH3,			18);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_B),	IOAPIC_ICH3,			19);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_C),	IOAPIC_ICH3,			16);	// Debug slot (J11)
 	smp_write_intsrc(mc, mp_INT,	MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW,	PCI_BUS_ICH3,		PCI_IRQ(2, INT_D),	IOAPIC_ICH3,			17);	// Debug slot (J11)
-	
+
 	// TODO: Not sure how to handle BT_INTR# signals from the P64H2s. Do we even need to, in APIC mode?
 
 	// Super I/O (ISA interrupts)
diff --git a/src/mainboard/intel/xe7501devkit/romstage.c b/src/mainboard/intel/xe7501devkit/romstage.c
index 003a37f31c..99f00212c1 100644
--- a/src/mainboard/intel/xe7501devkit/romstage.c
+++ b/src/mainboard/intel/xe7501devkit/romstage.c
@@ -48,7 +48,7 @@ static void main(unsigned long bist)
 		},
 	};
 
-	if (bist == 0) 
+	if (bist == 0)
 	{
 		// Skip this if there was a built in self test failure
 		early_mtrr_init();
@@ -68,14 +68,14 @@ static void main(unsigned long bist)
 
 	// If this is a warm boot, some initialization can be skipped
 
-	if (!bios_reset_detected()) 
+	if (!bios_reset_detected())
 	{
 		enable_smbus();
 		// dump_spd_registers(&memctrl[0]);
 		// dump_smbus_registers();
 		sdram_initialize(ARRAY_SIZE(memctrl), memctrl);
 	}
-	
+
 	// NOTE: ROMCC dies with an internal compiler error
 	//		 if the following line is removed.
 	print_debug("SDRAM is up.\n");