diff options
| author | Tobias Diedrich <ranma+coreboot@tdiedrich.de> | 2010-10-26 22:40:16 +0000 |
|---|---|---|
| committer | Uwe Hermann <uwe@hermann-uwe.de> | 2010-10-26 22:40:16 +0000 |
| commit | b907d321a5d0957f5cbb03d8f9c8d0ff0c23523b (patch) | |
| tree | ed994a792d00c4e97d85a2137a9f16f82c600a83 /src/mainboard/intel/xe7501devkit | |
| parent | 4a8d9938b24e54321b9b68e56af5ea4437cf65d5 (diff) | |
We need to call smp_write_lintsrc() instead of smp_write_intsrc() for
local ints. This is wrong in most coreboot mptables, probably all
generated by util/mptable/mptable.c.
After fixing this now XP can boot in MPS mode on my M2V.
Signed-off-by: Tobias Diedrich <ranma+coreboot@tdiedrich.de>
Acked-by: Uwe Hermann <uwe@hermann-uwe.de>
git-svn-id: svn://svn.coreboot.org/coreboot/trunk@5992 2b7e53f0-3cfb-0310-b3e9-8179ed1497e1
Diffstat (limited to 'src/mainboard/intel/xe7501devkit')
| -rw-r--r-- | src/mainboard/intel/xe7501devkit/mptable.c | 4 |
1 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/xe7501devkit/mptable.c b/src/mainboard/intel/xe7501devkit/mptable.c index 952fb6d978..9279b8485d 100644 --- a/src/mainboard/intel/xe7501devkit/mptable.c +++ b/src/mainboard/intel/xe7501devkit/mptable.c @@ -73,8 +73,8 @@ static void xe7501devkit_register_interrupts(struct mp_config_table *mc) { // Chipset PCI bus // Type Trigger | Polarity Bus ID IRQ APIC ID PIN# - smp_write_intsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); - smp_write_intsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); + smp_write_lintsrc(mc, mp_ExtINT, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 0); + smp_write_lintsrc(mc, mp_NMI, MP_IRQ_TRIGGER_EDGE |MP_IRQ_POLARITY_HIGH, PCI_BUS_CHIPSET, 0, MP_APIC_ALL, 1); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_A), IOAPIC_ICH3, 16); // USB 1.1 Controller #1 smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(31, INT_B), IOAPIC_ICH3, 17); // SMBus smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, PCI_BUS_CHIPSET, PCI_IRQ(29, INT_C), IOAPIC_ICH3, 18); // USB 1.1 Controller #3 |