diff options
| author | Patrick Georgi <pgeorgi@chromium.org> | 2015-12-12 00:23:15 +0100 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-01-21 19:40:57 +0100 |
| commit | 5d7ab39024705d872221aab126b42e743674d672 (patch) | |
| tree | 54591e9c78ecfaf380a750926e3632c4c4cd2452 /src/mainboard/intel/wtm2 | |
| parent | e02be0e14ab0d53fbe270556e1a7752558014b36 (diff) | |
chromeos: import Chrome OS fmaps
These are generated from depthcharge's board/*/fmap.dts using the
dts-to-fmd.sh script.
One special case is google/veyron's chromeos.fmd, which is used for a
larger set of boards - no problem since the converted fmd was the same
for all of them.
Set aside 128K for the bootblock on non-x86 systems (where the COREBOOT
region ends up at the beginning of flash). This becomes necessary
because we're working without a real cbfs master header (exists for
transition only), which carved out the space for the offset.
Change-Id: Ieeb33702d3e58e07e958523533f83da97237ecf1
Signed-off-by: Patrick Georgi <pgeorgi@chromium.org>
Reviewed-on: https://review.coreboot.org/12715
Tested-by: build bot (Jenkins)
Reviewed-by: Martin Roth <martinroth@google.com>
Diffstat (limited to 'src/mainboard/intel/wtm2')
| -rw-r--r-- | src/mainboard/intel/wtm2/chromeos.fmd | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/src/mainboard/intel/wtm2/chromeos.fmd b/src/mainboard/intel/wtm2/chromeos.fmd new file mode 100644 index 0000000000..5ac32447ec --- /dev/null +++ b/src/mainboard/intel/wtm2/chromeos.fmd @@ -0,0 +1,37 @@ +FLASH@0xff800000 0x800000 { + SI_ALL@0x0 0x180000 { + SI_DESC@0x0 0x1000 + SI_ME@0x1000 0x17f000 + } + SI_BIOS@0x180000 0x680000 { + RW_VPD@0x0 0x1000 + RW_UNUSED@0x1000 0x67000 + RW_SHARED@0x68000 0x18000 { + RW_ENVIRONMENT@0x0 0x4000 + RW_MRC_CACHE@0x4000 0x10000 + DEV_CFG@0x14000 0x4000 + } + RW_SECTION_A@0x80000 0x100000 { + VBLOCK_A@0x0 0x10000 + FW_MAIN_A(CBFS)@0x10000 0x7ffc0 + RW_FWID_A@0x8ffc0 0x40 + RW_UNUSED_A@0x90000 0x70000 + } + RW_SECTION_B@0x180000 0x100000 { + VBLOCK_B@0x0 0x10000 + FW_MAIN_B(CBFS)@0x10000 0x7ffc0 + RW_FWID_B@0x8ffc0 0x40 + RW_UNUSED_B@0x90000 0x70000 + } + RO_UNUSED_1@0x280000 0x170000 + RO_VPD@0x3f0000 0x20000 + RO_UNUSED_2@0x410000 0xe0000 + RO_SECTION@0x4f0000 0x190000 { + FMAP@0x0 0x800 + RO_FRID@0x800 0x40 + RO_PADDING@0x840 0xf7c0 + GBB@0x10000 0x80000 + COREBOOT(CBFS)@0x90000 0x100000 + } + } +} |