fox_wtm2: First step support for coreboot-based graphics startup

This code is the initial version of FUI for haswell and wtm2.

The code is simplified from before in many ways. I've gotten rid of
the opcode table, because it obscured meaning and I don't think it is
needed any more. Register sets, mainly used for reset, are just lines
of code -- not many of them. There are a bunch of not-yet-documented
registers here; the VBIOS seemed to think they were necessary and
testing shows they seem to be right.

As a bit of added paranoia, we always include the VBIOS code as our
emergency recovery path. You have to run it now anyways, so this is no
regression from our current situation; and, if all goes well, in a
week (or so), you'll never have to run it again, but like the Force
and nose hair, it will be with you always.

The code can return in three ways. The first, best way is success:
panel is up and the VBIOS need not run. The second mode is that we
tried to light up the panel but could not, for some reason, but will
return with the panel partly up. In this case, it's ok not to power
cycle the panel. The third, worst case, which will NEVER happen, ha
ha, is that we have to turn the panel off and wait the required 600ms
for it to cycle. Life sucks sometimes. This failure mode is in the
'hang on we're going to fix it' category now that we have ramstage in
RW.

The Big Goal here is to create something other coreboot ports can use
as well. The guys doing the x60 report that the link FUI works,
without too many mods, on that chipset, so it seems Intel is keeping
things from changing too much over time.

Also, again, please note: this and the next 3 versions will ALWAYS fail.
The goal is to verify the correctness of the recovery path.

The bizarre tab-space formatting in drm_dp_helper.h is from the original,
as in i915_reg.h

Change-Id: I6ecf454633029d185c29d470980b5a0f3114a8ce
Signed-off-by: Ronald G. Minnich <rminnich@google.com>
Signed-off-by: Gabe Black <gabeblack@chromium.org>
Reviewed-on: http://review.coreboot.org/3635
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 89 insertions, 0 deletions

diff --git a/src/mainboard/intel/wtm2/graphics.c b/src/mainboard/intel/wtm2/graphics.c
new file mode 100644
index 0000000000..79820b9fe9
--- /dev/null
+++ b/src/mainboard/intel/wtm2/graphics.c
@@ -0,0 +1,89 @@
+/*
+* This file is part of the coreboot project.
+*
+* Copyright 2013 Google Inc.
+*
+* This program is free software; you can redistribute it and/or modify
+* it under the terms of the GNU General Public License as published by
+* the Free Software Foundation; version 2 of the License.
+*
+* This program is distributed in the hope that it will be useful,
+* but WITHOUT ANY WARRANTY; without even the implied warranty of
+* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+* GNU General Public License for more details.
+*
+* You should have received a copy of the GNU General Public License
+* along with this program; if not, write to the Free Software
+* Foundation, Inc., 51 Franklin St, Fifth Floor, Boston, MA 02110-1301 USA
+*/
+/* this file was for the most part machine generated, and in future
+ * will be all machine generated. Avoid editing.
+ */
+#include <console/console.h>
+#include "i915io.h"
+
+void graphics_register_reset(u32 aux_ctl, u32 aux_data, int verbose)
+{
+
+	io_i915_write32(0x80000000,0x45400);
+	io_i915_write32(0x00000000,_CURACNTR);
+	io_i915_write32((/* PIPEA */0x0<<24)|0x00000000,_DSPACNTR);
+	io_i915_write32(0x00000000,_DSPBCNTR);
+	io_i915_write32(0x80000000,CPU_VGACNTRL);
+	io_i915_write32(0x00000000,_DSPASIZE+0xc);
+	io_i915_write32(0x00000000,_DSPBSURF);
+	io_i915_write32(0x00000000,0x4f050);
+	io_i915_write32( DP_LINK_TRAIN_PAT_1 | DP_LINK_TRAIN_PAT_1_CPT |
+		DP_VOLTAGE_0_4 | DP_PRE_EMPHASIS_0 | DP_PORT_WIDTH_1 |
+		DP_PLL_FREQ_270MHZ | DP_SCRAMBLING_DISABLE_IRONLAKE |
+		DP_SYNC_VS_HIGH |0x00000091,DP_A);
+	io_i915_write32(0x00200090,_FDI_RXA_MISC);
+	io_i915_write32(0x0a000000,_FDI_RXA_MISC);
+	/* not yet documented anywhere that we can find. */
+	io_i915_write32(0x00000070,0x46408);
+	io_i915_write32(0x04000000,0x42090);
+	io_i915_write32(0x40000000,0x4f050);
+	io_i915_write32(0x00000000,0x9840);
+	io_i915_write32(0xa4000000,0x42090);
+	io_i915_write32(0x00004000,0x42080);
+	io_i915_write32(0x00ffffff,0x64f80);
+	io_i915_write32(0x0007000e,0x64f84);
+	io_i915_write32(0x00d75fff,0x64f88);
+	io_i915_write32(0x000f000a,0x64f8c);
+	io_i915_write32(0x00c30fff,0x64f90);
+	io_i915_write32(0x00060006,0x64f94);
+	io_i915_write32(0x00aaafff,0x64f98);
+	io_i915_write32(0x001e0000,0x64f9c);
+	io_i915_write32(0x00ffffff,0x64fa0);
+	io_i915_write32(0x000f000a,0x64fa4);
+	io_i915_write32(0x00d75fff,0x64fa8);
+	io_i915_write32(0x00160004,0x64fac);
+	io_i915_write32(0x00c30fff,0x64fb0);
+	io_i915_write32(0x001e0000,0x64fb4);
+	io_i915_write32(0x00ffffff,0x64fb8);
+	io_i915_write32(0x00060006,0x64fbc);
+	io_i915_write32(0x00d75fff,0x64fc0);
+	io_i915_write32(0x001e0000,0x64fc4);
+	io_i915_write32(0x00ffffff,0x64e00);
+	io_i915_write32(0x0006000e,0x64e04);
+	io_i915_write32(0x00d75fff,0x64e08);
+	io_i915_write32(0x0005000a,0x64e0c);
+	io_i915_write32(0x00c30fff,0x64e10);
+	io_i915_write32(0x00040006,0x64e14);
+	io_i915_write32(0x80aaafff,0x64e18);
+	io_i915_write32(0x000b0000,0x64e1c);
+	io_i915_write32(0x00ffffff,0x64e20);
+	io_i915_write32(0x0005000a,0x64e24);
+	io_i915_write32(0x00d75fff,0x64e28);
+	io_i915_write32(0x000c0004,0x64e2c);
+	io_i915_write32(0x80c30fff,0x64e30);
+	io_i915_write32(0x000b0000,0x64e34);
+	io_i915_write32(0x00ffffff,0x64e38);
+	io_i915_write32(0x00040006,0x64e3c);
+	io_i915_write32(0x80d75fff,0x64e40);
+	io_i915_write32(0x000b0000,0x64e44);
+	/* end not yet documented. */
+	io_i915_write32(0x10000000,SDEISR+0x30);
+}
+
+