Add Intel Whitetip Mountain 2 mainboard

This is mostly a copy of Whitetip Mountain 1 with specific GPIO
map for this Customer Reference Board (CRB).

This mainboard currently has basic funcionality and is able to
boot a Linux Kernel but many of the new Haswell ULT specific
devices are not yet enabled.

Change-Id: I999452d86f00a2c245fa39b1b76080f6a3b1e352
Signed-off-by: Duncan Laurie <dlaurie@chromium.org>
Reviewed-on: http://review.coreboot.org/2725
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Tested-by: build bot (Jenkins)
Reviewed-by: Ronald G. Minnich <rminnich@gmail.com>

1 files changed, 37 insertions, 0 deletions

diff --git a/src/mainboard/intel/wtm2/acpi/ec.asl b/src/mainboard/intel/wtm2/acpi/ec.asl
new file mode 100644
index 0000000000..9ae5951aca
--- /dev/null
+++ b/src/mainboard/intel/wtm2/acpi/ec.asl
@@ -0,0 +1,37 @@
+Device (EC0)
+{
+	Name (_HID, EISAID ("PNP0C09"))
+	Name (_UID, 1)
+	Name (_GPE, 10) // GPIO 10 is SMC_RUNTIME_SCI_N
+
+	OperationRegion (ERAM, EmbeddedControl, 0x00, 0xff)
+	Field (ERAM, ByteAcc, Lock, Preserve)
+	{
+		Offset (0x03),
+		ACPR, 1,	// AC Power (1=present)
+		    , 2,
+		CFAN, 1,	// CPU Fan (1=on)
+		    , 2,
+		LIDS, 1,	// Lid State (1=open)
+		    , 1,
+		SPTR, 8,	// SMBUS Protocol Register
+		SSTS, 8,	// SMBUS Status Register
+		SADR, 8,	// SMBUS Address Register
+		SCMD, 8,	// SMBUS Command Register
+		SBFR, 256,	// SMBUS Block Buffer
+		SCNT, 8,	// SMBUS Block Count
+
+		Offset (0x3a),
+		ECMD, 8,	// EC Command Register
+
+		Offset (0x82),
+		PECL, 8,	// PECI fractional (1/64 Celsius)
+		PECH, 8,	// PECI integer (Celsius)
+	}
+
+	Name (_CRS, ResourceTemplate()
+	{
+		IO (Decode16, 0x62, 0x62, 0, 1)
+		IO (Decode16, 0x66, 0x66, 0, 1)
+	})
+}