diff options
| author | Elyes HAOUAS <ehaouas@noos.fr> | 2016-09-19 09:46:33 -0600 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2016-09-20 21:54:45 +0200 |
| commit | 531b87ac4e8038aedf9c44c29fe2c1fc31adb346 (patch) | |
| tree | 0beaa7220a61927e2bc0a4d59eb1827b73fe6c02 /src/mainboard/intel/truxton | |
| parent | 04f8fd981fd49e9929fea2b27991e78673fc57a3 (diff) | |
src/mainboard/getac - kontron: Add space around operators
Change-Id: If3cdfdff60c92e3427f1b285e2bca92e2bb2a1cb
Signed-off-by: Elyes HAOUAS <ehaouas@noos.fr>
Reviewed-on: https://review.coreboot.org/16640
Tested-by: build bot (Jenkins)
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Diffstat (limited to 'src/mainboard/intel/truxton')
| -rw-r--r-- | src/mainboard/intel/truxton/mptable.c | 34 |
1 files changed, 17 insertions, 17 deletions
diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c index f6cf1cfc09..ca934b3aee 100644 --- a/src/mainboard/intel/truxton/mptable.c +++ b/src/mainboard/intel/truxton/mptable.c @@ -75,50 +75,50 @@ static void *smp_write_config_table(void *v) /* IMCH/IICH PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01<<2)|0, 0x8, 0x10); /* DMA controller */ + 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02<<2)|0, 0x8, 0x10); /* PCIe port A bridge */ + 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03<<2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ + 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x04<<2)|0, 0x8, 0x10); /* AIOC PCI bridge */ + 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d<<2)|0, 0x8, 0x10); /* UHCI/EHCI */ + 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f<<2)|1, 0x8, 0x11); /* SATA/SMBus */ + 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */ if (bus_pea0) { /* PCIe slot 0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|0, 0x8, 0x10); + bus_pea0, (0 << 2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|1, 0x8, 0x11); + bus_pea0, (0 << 2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|2, 0x8, 0x12); + bus_pea0, (0 << 2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0<<2)|3, 0x8, 0x13); + bus_pea0, (0 << 2)|3, 0x8, 0x13); } if (bus_pea1) { /* PCIe slots 1-4 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|0, 0x8, 0x10); + bus_pea1, (0 << 2)|0, 0x8, 0x10); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|1, 0x8, 0x11); + bus_pea1, (0 << 2)|1, 0x8, 0x11); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|2, 0x8, 0x12); + bus_pea1, (0 << 2)|2, 0x8, 0x12); smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0<<2)|3, 0x8, 0x13); + bus_pea1, (0 << 2)|3, 0x8, 0x13); } if (bus_aioc) { /* AIOC PCI devices */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (0<<2)|0, 0x8, 0x10); /* GbE0 */ + bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (1<<2)|0, 0x8, 0x11); /* GbE1 */ + bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */ smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (2<<2)|0, 0x8, 0x12); /* GbE2 */ + bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */ } /* There is no extension information... */ |