diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/mainboard/intel/truxton | |
parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel/truxton')
-rw-r--r-- | src/mainboard/intel/truxton/Kconfig | 31 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/Kconfig.name | 2 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/Makefile.inc | 1 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/board_info.txt | 3 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/devicetree.cb | 55 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/irq_tables.c | 39 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/mptable.c | 135 | ||||
-rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 86 |
8 files changed, 0 insertions, 352 deletions
diff --git a/src/mainboard/intel/truxton/Kconfig b/src/mainboard/intel/truxton/Kconfig deleted file mode 100644 index cd8e478f1b..0000000000 --- a/src/mainboard/intel/truxton/Kconfig +++ /dev/null @@ -1,31 +0,0 @@ -if BOARD_INTEL_TRUXTON - -config BOARD_SPECIFIC_OPTIONS # dummy - def_bool y - select CPU_INTEL_EP80579 - select NORTHBRIDGE_INTEL_I3100 - select SOUTHBRIDGE_INTEL_I3100 - select SUPERIO_INTEL_I3100 - select SUPERIO_SMSC_SMSCSUPERIO - select HAVE_HARD_RESET - select HAVE_PIRQ_TABLE - select HAVE_MP_TABLE - select BOARD_ROMSIZE_KB_2048 - -config MAINBOARD_DIR - string - default intel/truxton - -config MAINBOARD_PART_NUMBER - string - default "Truxton" - -config IRQ_SLOT_COUNT - int - default 1 - -config MAX_CPUS - int - default 4 - -endif # BOARD_INTEL_TRUXTON diff --git a/src/mainboard/intel/truxton/Kconfig.name b/src/mainboard/intel/truxton/Kconfig.name deleted file mode 100644 index f91b44538f..0000000000 --- a/src/mainboard/intel/truxton/Kconfig.name +++ /dev/null @@ -1,2 +0,0 @@ -config BOARD_INTEL_TRUXTON - bool "EP80579 devkit (Truxton)" diff --git a/src/mainboard/intel/truxton/Makefile.inc b/src/mainboard/intel/truxton/Makefile.inc deleted file mode 100644 index 6ef4fc9d50..0000000000 --- a/src/mainboard/intel/truxton/Makefile.inc +++ /dev/null @@ -1 +0,0 @@ -ROMCCFLAGS := -mcpu=p4 -fno-simplify-phi -O2 diff --git a/src/mainboard/intel/truxton/board_info.txt b/src/mainboard/intel/truxton/board_info.txt deleted file mode 100644 index 5ae0fde757..0000000000 --- a/src/mainboard/intel/truxton/board_info.txt +++ /dev/null @@ -1,3 +0,0 @@ -Board name: EP80579 devkit (Truxton) -Category: eval -Release year: 2009 diff --git a/src/mainboard/intel/truxton/devicetree.cb b/src/mainboard/intel/truxton/devicetree.cb deleted file mode 100644 index 05fb05ecf1..0000000000 --- a/src/mainboard/intel/truxton/devicetree.cb +++ /dev/null @@ -1,55 +0,0 @@ -chip northbridge/intel/i3100 - device domain 0 on - subsystemid 0x8086 0x2680 inherit - device pci 00.0 on end # IMCH - device pci 00.1 on end # IMCH error status - device pci 01.0 on end # IMCH EDMA engine - device pci 02.0 on end # PCIe port A/A0 - device pci 03.0 on end # PCIe port A1 - device pci 04.0 on end # ? - device pci 08.0 off end # must be off to boot - device pci 0d.0 off end # must be off to boot - device pci 0d.1 off end # must be off to boot - chip southbridge/intel/i3100 - # PIRQ line -> legacy IRQ mappings - register "pirq_a_d" = "0x0b070a05" - register "pirq_e_h" = "0x0a808080" - - device pci 1d.0 on end # USB (UHCI) - device pci 1d.7 on end # USB (EHCI) - device pci 1f.0 on # LPC bridge - chip superio/intel/i3100 - device pnp 4e.4 on # Com1 - io 0x60 = 0x3f8 - irq 0x70 = 4 - end - device pnp 4e.5 on # Com2 - io 0x60 = 0x2f8 - irq 0x70 = 3 - end - end - chip superio/smsc/smscsuperio - device pnp 2e.0 off end - device pnp 2e.3 off end - device pnp 2e.4 off end - device pnp 2e.5 off end - device pnp 2e.7 on # PS/2 keyboard / mouse - io 0x60 = 0x60 - io 0x62 = 0x64 - irq 0x70 = 1 # PS/2 keyboard interrupt - irq 0x72 = 12 # PS/2 mouse interrupt - end - device pnp 2e.a off end - end - end - device pci 1f.2 on end # SATA - device pci 1f.3 on end # SMBus - device pci 1f.4 on end # ? - end - end - device cpu_cluster 0 on - chip cpu/intel/ep80579 - device lapic 0 on end - end - end -end diff --git a/src/mainboard/intel/truxton/irq_tables.c b/src/mainboard/intel/truxton/irq_tables.c deleted file mode 100644 index c34809f677..0000000000 --- a/src/mainboard/intel/truxton/irq_tables.c +++ /dev/null @@ -1,39 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - */ - -#include <arch/pirq_routing.h> - -static const struct irq_routing_table intel_irq_routing_table = { - PIRQ_SIGNATURE, /* u32 signature */ - PIRQ_VERSION, /* u16 version */ - 32+16*CONFIG_IRQ_SLOT_COUNT, /* u16 Table size 32+(16*devices) */ - 0x00, /* u8 Bus 0 */ - (0x1f << 3) | 0x0, /* u8 Device 1f, Function 0 */ - 0x0000, /* u16 reserve IRQ for PCI */ - 0x8086, /* u16 Vendor */ - 0x5031, /* Device ID */ - 0x00000000, /* u32 miniport_data */ - { 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0 }, /* u8 rfu[11] */ - 0x5e, /* u8 checksum - mod 256 checksum must give zero */ - { /* bus, devfn, {link, bitmap}, {link, bitmap}, {link, bitmap}, {link, bitmap}, slot, rfu */ - {0x00, 0xf8, {{0x62, 0xdc78}, {0x61, 0xdcf8}, {0x00, 0x0000}, {0x00, 0x0000}}, 0x00, 0x00}, - } -}; - -unsigned long write_pirq_routing_table(unsigned long addr) -{ - return copy_pirq_routing_table(addr, &intel_irq_routing_table); -} diff --git a/src/mainboard/intel/truxton/mptable.c b/src/mainboard/intel/truxton/mptable.c deleted file mode 100644 index ca934b3aee..0000000000 --- a/src/mainboard/intel/truxton/mptable.c +++ /dev/null @@ -1,135 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <console/console.h> -#include <arch/smp/mpspec.h> -#include <arch/ioapic.h> -#include <device/pci.h> -#include <string.h> -#include <stdint.h> - -static void *smp_write_config_table(void *v) -{ - struct mp_config_table *mc; - int bus_isa; - u8 bus_pea0 = 0; - u8 bus_pea1 = 0; - u8 bus_aioc; - device_t dev; - - mc = (void *)(((char *)v) + SMP_FLOATING_TABLE_LEN); - - mptable_init(mc, LOCAL_APIC_ADDR); - - smp_write_processors(mc); - - /* AIOC bridge */ - dev = dev_find_slot(0, PCI_DEVFN(0x04,0)); - if (dev) { - bus_aioc = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:04.0\n"); - bus_aioc = 0; - } - /* PCIe A0 */ - dev = dev_find_slot(0, PCI_DEVFN(0x02,0)); - if (dev) { - bus_pea0 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:02.0\n"); - bus_pea0 = 0; - } - /* PCIe A1 */ - dev = dev_find_slot(0, PCI_DEVFN(0x03,0)); - if (dev) { - bus_pea1 = pci_read_config8(dev, PCI_SECONDARY_BUS); - } - else { - printk(BIOS_DEBUG, "ERROR - could not find PCI 0:03.0\n"); - bus_pea1 = 0; - } - - mptable_write_buses(mc, NULL, &bus_isa); - - /* IOAPIC handling */ - smp_write_ioapic(mc, 0x8, 0x20, VIO_APIC_VADDR); - - mptable_add_isa_interrupts(mc, bus_isa, 0x8, 0); - - /* Standard local interrupt assignments */ - mptable_lintsrc(mc, bus_isa); - - /* IMCH/IICH PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x01 << 2)|0, 0x8, 0x10); /* DMA controller */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x02 << 2)|0, 0x8, 0x10); /* PCIe port A bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x03 << 2)|0, 0x8, 0x10); /* PCIe port A1 bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x04 << 2)|0, 0x8, 0x10); /* AIOC PCI bridge */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1d << 2)|0, 0x8, 0x10); /* UHCI/EHCI */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_LEVEL|MP_IRQ_POLARITY_LOW, - 0, (0x1f << 2)|1, 0x8, 0x11); /* SATA/SMBus */ - - if (bus_pea0) { - /* PCIe slot 0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|0, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|1, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|2, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea0, (0 << 2)|3, 0x8, 0x13); - } - - if (bus_pea1) { - /* PCIe slots 1-4 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|0, 0x8, 0x10); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|1, 0x8, 0x11); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|2, 0x8, 0x12); - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_pea1, (0 << 2)|3, 0x8, 0x13); - } - - if (bus_aioc) { - /* AIOC PCI devices */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (0 << 2)|0, 0x8, 0x10); /* GbE0 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (1 << 2)|0, 0x8, 0x11); /* GbE1 */ - smp_write_intsrc(mc, mp_INT, MP_IRQ_TRIGGER_DEFAULT|MP_IRQ_POLARITY_DEFAULT, - bus_aioc, (2 << 2)|0, 0x8, 0x12); /* GbE2 */ - } - - /* There is no extension information... */ - - /* Compute the checksums */ - return mptable_finalize(mc); -} - -unsigned long write_smp_table(unsigned long addr) -{ - void *v; - v = smp_write_floating_table(addr, 0); - return (unsigned long)smp_write_config_table(v); -} diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c deleted file mode 100644 index 4b64210c38..0000000000 --- a/src/mainboard/intel/truxton/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include <northbridge/intel/i3100/raminit_ep80579.h> -#include <superio/intel/i3100/i3100.h> -#include "lib/debug.c" // XXX -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <spd.h> - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i3100/raminit_ep80579.c" -#include "lib/generic_sdram.c" - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .channel0 = { DIMM2, DIMM3 }, - } - }; - - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - if (memory_initialized()) - return; - } - - /* Set up the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - -#ifdef TRUXTON_DEBUG - print_pci_devices(); -#endif - enable_smbus(); - - sdram_initialize(ARRAY_SIZE(mch), mch); - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0x00, 0)); -#ifdef TRUXTON_DEBUG - dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} |