diff options
author | Martin Roth <gaumless@gmail.com> | 2017-10-15 15:06:48 -0600 |
---|---|---|
committer | Martin Roth <martinroth@google.com> | 2018-01-15 23:25:12 +0000 |
commit | 264566c177dac98e67c2a4765fe08c5d8de10753 (patch) | |
tree | 34cfe5ba3958d14dd976bd7f2a2fb58a3920c74d /src/mainboard/intel/truxton/romstage.c | |
parent | f6af8943e23b8ffa27df6ddb8e4a654387be0cb6 (diff) |
Intel i3100 boards & chips: Remove - using LATE_CBMEM_INIT
All boards and chips that are still using LATE_CBMEM_INIT are being
removed as previously discussed.
If these boards and chips are updated to not use LATE_CBMEM_INIT, they
can be restored to the active codebase from the 4.7 branch.
chips:
northbridge/intel/i3100
southbridge/intel/i3100
superio/intel/i3100
cpu/intel/socket_mPGA479M
Mainboards:
mainboard/intel/truxton
mainboard/intel/mtarvon
mainboard/intel/truxton
Change-Id: Ic2bbdc8ceb3ba0359c120cf4286b0c5b7dc653bb
Signed-off-by: Martin Roth <gaumless@gmail.com>
Reviewed-on: https://review.coreboot.org/22031
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Diffstat (limited to 'src/mainboard/intel/truxton/romstage.c')
-rw-r--r-- | src/mainboard/intel/truxton/romstage.c | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/src/mainboard/intel/truxton/romstage.c b/src/mainboard/intel/truxton/romstage.c deleted file mode 100644 index 4b64210c38..0000000000 --- a/src/mainboard/intel/truxton/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2008 Arastra, Inc. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <stdlib.h> -#include <device/pci_def.h> -#include <device/pci_ids.h> -#include <arch/io.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <pc80/mc146818rtc.h> -#include <console/console.h> -#include "southbridge/intel/i3100/early_smbus.c" -#include "southbridge/intel/i3100/early_lpc.c" -#include <northbridge/intel/i3100/raminit_ep80579.h> -#include <superio/intel/i3100/i3100.h> -#include "lib/debug.c" // XXX -#include <cpu/x86/bist.h> -#include <cpu/intel/romstage.h> -#include <spd.h> - -#define DEVPRES_CONFIG (DEVPRES_D1F0 | DEVPRES_D2F0 | DEVPRES_D3F0 | DEVPRES_D4F0) - -static inline int spd_read_byte(u16 device, u8 address) -{ - return smbus_read_byte(device, address); -} - -#include "northbridge/intel/i3100/raminit_ep80579.c" -#include "lib/generic_sdram.c" - -#define SERIAL_DEV PNP_DEV(0x4e, I3100_SP1) - -void mainboard_romstage_entry(unsigned long bist) -{ - static const struct mem_controller mch[] = { - { - .node_id = 0, - .f0 = PCI_DEV(0, 0x00, 0), - .channel0 = { DIMM2, DIMM3 }, - } - }; - - if (bist == 0) { - /* Skip this if there was a built in self test failure */ - if (memory_initialized()) - return; - } - - /* Set up the console */ - i3100_enable_superio(); - i3100_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i3100_configure_uart_clk(SERIAL_DEV, I3100_UART_CLK_PREDIVIDE_26); - - console_init(); - - /* Prevent the TCO timer from rebooting us */ - i3100_halt_tco_timer(); - - /* Halt if there was a built in self test failure */ - report_bist_failure(bist); - -#ifdef TRUXTON_DEBUG - print_pci_devices(); -#endif - enable_smbus(); - - sdram_initialize(ARRAY_SIZE(mch), mch); - dump_pci_devices(); - dump_pci_device(PCI_DEV(0, 0x00, 0)); -#ifdef TRUXTON_DEBUG - dump_bar14(PCI_DEV(0, 0x00, 0)); -#endif -} |