diff options
| author | Felix Singer <felixsinger@posteo.net> | 2021-12-05 02:40:26 +0100 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2021-12-09 21:52:13 +0000 |
| commit | 715b787fd3d1a0e714da795ea3d3eaf28ca49577 (patch) | |
| tree | 36bddb19913ef007da7ba6d4aa29758e21ca189f /src/mainboard/intel/tglrvp | |
| parent | 2bf2e6d1ccd87cdd8d9c189972eae89e47e542c8 (diff) | |
soc/intel/tigerlake: Hook up SMBus device to devicetree
Hook up `SmbusEnable` FSP setting to devicetree state and drop its
redundant devicetree setting `SmbusEnable`.
The following mainboards enable the SMBus device in the devicetree
despite `SmbusEnable` is not being set.
* google/deltaur
* starlabs/laptop
Thus, set it to off to keep the current state unchanged.
Change-Id: I0789af20beb147fc1a6a7d046cdcea15cb44ce4c
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/59883
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 1 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 1 |
2 files changed, 0 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index b84fddc397..0e34eb2663 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -13,7 +13,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Enabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index fcadcee990..17af01aaeb 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -13,7 +13,6 @@ chip soc/intel/tigerlake # FSP configuration register "SaGv" = "SaGv_Disabled" - register "SmbusEnable" = "1" # CNVi BT enable/disable register "CnviBtCore" = "true" |