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| author | Lean Sheng Tan <sheng.tan@9elements.com> | 2022-05-18 17:35:31 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-20 11:20:46 +0000 |
| commit | 100514d8c7fdfea17de938cddc63f1457dd3af3a (patch) | |
| tree | b6df201fa92cfd5e96ce8f59f6cc0b2304378a00 /src/mainboard/intel/tglrvp | |
| parent | a68824185eeff91b89bf4d899b3a90f454365d0a (diff) | |
soc/intel/ehl: Fix logical bug for PseTsnGbePhyInterfaceType
By right if PseTsnGbeSgmiiEnable is disable,
PseTsnGbePhyInterfaceType should use RGMII setting.
Signed-off-by: Lean Sheng Tan <sheng.tan@9elements.com>
Change-Id: If593a5534716a9e93f99cb155fb5e86e12b1df17
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64477
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Mario Scheithauer <mario.scheithauer@siemens.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp')
0 files changed, 0 insertions, 0 deletions