diff options
| author | Wonkyu Kim <wonkyu.kim@intel.com> | 2020-01-23 00:12:46 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-01-28 18:37:03 +0000 |
| commit | 46cef44dad8f796b9c5ac0ed3a684266b88cec62 (patch) | |
| tree | ea68f2d5d03ab484fdb63e399819d4677dce48c7 /src/mainboard/intel/tglrvp | |
| parent | 9f2e3ad6280000b818c71ebd250430509a819553 (diff) | |
mb/intel/tglrvp: Enable DP ports for TGLRVP
TGLRVP uses DdiPort1Hpd and DdiPort1Ddc. So only enable them.
BUG=none
BRANCH=none
TEST=Build and boot tigerlake rvp board and check FSP log or DP port pin mux
from pinctl driver.
Signed-off-by: Wonkyu Kim <wonkyu.kim@intel.com>
Change-Id: Ief6376ba59c77340e272923958b6b5f0a1456d9b
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38529
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index e7bfe337f9..d4b5a39bfd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -49,6 +49,12 @@ chip soc/intel/tigerlake register "SataPortsEnable[0]" = "1" register "SataPortsEnable[1]" = "1" + # enabling EDP in PortA + register "DdiPortAConfig" = "1" + + register "DdiPort1Hpd" = "1" + register "DdiPort1Ddc" = "1" + register "SerialIoI2cMode" = "{ [PchSerialIoIndexI2C0] = PchSerialIoPci, [PchSerialIoIndexI2C1] = PchSerialIoPci, |