diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2022-05-04 17:08:11 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2022-05-05 17:38:14 +0000 |
| commit | da4e1d780656d6a733f7c2445697466c86a8e901 (patch) | |
| tree | 306e6df6215c3445eb58bd0a677df6da2c52cba6 /src/mainboard/intel/tglrvp/variants | |
| parent | 7fd65e9b3abd0c0f0359d0d91baf27a441ceaab6 (diff) | |
soc/intel/tigerlake: Add enum for `DdiPortXConfig`
Add an enum for `DdiPortXConfig` devicetree options. Note that setting
these options to zero does not disable the corresponding DDI port, but
instead indicates that no LFP (Local Flat Panel, i.e. internal LCD) is
connected to it.
Change-Id: I9ea10141e51bf29ea44199dcd1b55b63ec771c0a
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/64047
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Reviewed-by: Tim Crawford <tcrawford@system76.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 2c9a548ae0..1af05c49cd 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -68,7 +68,7 @@ chip soc/intel/tigerlake register "SataPortsEnable[1]" = "1" # enabling EDP in PortA - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortBHpd" = "1" register "DdiPort1Hpd" = "1" diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb index d19747a5c0..ad1a45d2e7 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb @@ -65,7 +65,7 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[3]" = "0x8" # enabling EDP in PortA - register "DdiPortAConfig" = "1" + register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" register "DdiPortAHpd" = "1" register "DdiPortADdc" = "0" |