mb/intel/tglrvp: add Tiger Lake memory initialization support

Update memory parameters based on memory type supported by Tiger lake RVP
1. Update dq/dqs mappings
2. Update spd data for Tiger lake LPDDR4 SAMSUNG/MICRON memory
3. Add SPD data bin files for supported memory types
4. Update other FSPM UPDs as part of memory initialization

BUG=none
BRANCH=none
TEST= build tglrvp flash and boot to kernel

Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I7248862efd1dcd5a0df0e17d39b44c168caa200e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/38998
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>

3 files changed, 67 insertions, 2 deletions

diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
index 9220b1140c..25c9755d9d 100644
--- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
+++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/variants.h
@@ -1,7 +1,7 @@
 /*
  * This file is part of the coreboot project.
  *
- * Copyright (C) 2019 Intel Corporation.
+ * Copyright (C) 2019-2020 Intel Corporation.
  *
  * This program is free software; you can redistribute it and/or modify
  * it under the terms of the GNU General Public License as published by
@@ -17,6 +17,7 @@
 #define __BASEBOARD_VARIANTS_H__
 
 #include <soc/gpio.h>
+#include <soc/meminit_tgl.h>
 #include <stdint.h>
 #include <vendorcode/google/chromeos/chromeos.h>
 
@@ -27,4 +28,7 @@ const struct pad_config *variant_gpio_table(size_t *num);
 const struct pad_config *variant_early_gpio_table(size_t *num);
 const struct cros_gpio *variant_cros_gpios(size_t *num);
 
+size_t variant_memory_sku(void);
+const struct mb_lpddr4x_cfg *variant_memory_params(void);
+
 #endif /*__BASEBOARD_VARIANTS_H__ */
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
index 23bf160883..c272607042 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/Makefile.inc
@@ -1,7 +1,7 @@
 ##
 ## This file is part of the coreboot project.
 ##
-## Copyright (C) 2019 Intel Corporation.
+## Copyright (C) 2019-2020 Intel Corporation.
 ##
 ## This program is free software; you can redistribute it and/or modify
 ## it under the terms of the GNU General Public License as published by
@@ -15,4 +15,6 @@
 
 bootblock-y += gpio.c
 
+romstage-y += memory.c
+
 ramstage-y += gpio.c
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
new file mode 100644
index 0000000000..67979b649b
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/memory.c
@@ -0,0 +1,59 @@
+/*
+ * This file is part of the coreboot project.
+ *
+ * Copyright (C) 2020 Intel Corporation.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; version 2 of the License.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ */
+
+#include <arch/cpu.h>
+#include <baseboard/variants.h>
+#include <intelblocks/mp_init.h>
+
+size_t __weak variant_memory_sku(void)
+{
+	return 0;
+}
+
+static const struct mb_lpddr4x_cfg mem_config = {
+	/* DQ byte map */
+	.dq_map = {
+	{  0,  1,  6,  7,  3,  2,  5,  4,    /* Byte 0 */
+	  15,  8,  9, 14, 12, 11, 10, 13 },  /* Byte 1 */
+	{ 11, 12,  8, 15,  9, 14, 10, 13,    /* Byte 2 */
+	   3,  4,  7,  0,  6,  1,  5,  2 },  /* Byte 3 */
+	{  4,  5,  3,  2,  7,  1,  0,  6,    /*	Byte 4 */
+	  11, 10, 12, 13,  8,  9, 14, 15 },  /* Byte 5 */
+	{ 12, 11,  8, 13, 14, 15,  9, 10,    /* Byte 6 */
+	   4,  7,  3,  2,  1,  6,  0,  5 },  /* Byte 7 */
+	{ 11, 10,  9,  8, 12, 13, 15, 14,    /* Byte 0 */
+	   4,  5,  6,  7,  3,  2,  0,  1 },  /* Byte 1 */
+	{  0,  7,  1,  6,  3,  5,  2,  4,    /* Byte 2 */
+	   9,  8, 10, 11, 14, 15, 13, 12 },  /* Byte 3 */
+	{  4,  5,  6,  1,  3,  2,  7,  0,    /* Byte 4 */
+	  10, 13, 12, 11, 14,  9, 15,  8 },  /* Byte 5 */
+	{ 10, 12,  9, 15,  8, 11, 13, 14,    /* Byte 6 */
+	   3,  4,  1,  2,  6,  0,  5,  7 }   /* Byte 7 */
+	},
+
+	/* DQS CPU<>DRAM map */
+	.dqs_map = {
+	/* Ch 0     1         2         3  */
+	{ 0, 1 }, { 1, 0 }, { 0, 1 }, { 1, 0 },
+	{ 1, 0 }, { 0, 1 }, { 0, 1 }, { 1, 0 }
+	},
+
+	.ect = 1, /* Early Command Training */
+};
+
+const struct mb_lpddr4x_cfg *__weak variant_memory_params(void)
+{
+	return &mem_config;
+}