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| author | John Zhao <john.zhao@intel.com> | 2020-05-16 13:06:25 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-05-26 15:07:07 +0000 |
| commit | 8aac881fe8caacd264fe6e0951750c6357bb3b5c (patch) | |
| tree | 88e08d00063c0d683b0a9e0a8ea6baa7d250fedc /src/mainboard/intel/tglrvp/variants | |
| parent | 1408798637125f1707ded7215e22461c623a79a8 (diff) | |
soc/intel/tigerlake: Add FSP UPD D3HotEnable and D3ColdEnable
This adds FSP UPD D3HotEnable and D3ColdEnable for configuration.
D3Hot low power mode support is for TCSS xhci, xdci, TBT PCIe root
ports and DMA controllers. D3Cold is lower mode for TBT PCIe root
ports and DMA controllers with D3Hot->D3Cold transition.
BUG=:b:146624360
TEST=Built and booted on Volteer.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: I6782cde6a1bfe13f46e75db8c85537c6d62f5d41
Reviewed-on: https://review.coreboot.org/c/coreboot/+/41474
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Furquan Shaikh <furquan@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
0 files changed, 0 insertions, 0 deletions