summaryrefslogtreecommitdiff
path: root/src/mainboard/intel/tglrvp/variants
diff options
context:
space:
mode:
authorTim Wawrzynczak <twawrzynczak@chromium.org>2020-09-30 13:59:21 -0600
committerTim Wawrzynczak <twawrzynczak@chromium.org>2020-10-30 15:23:58 +0000
commiteafe7989ace4e5d0b4214b6b30467438da3965ff (patch)
tree05fac8f55efcb5a8d1e45156e84ce691dcab7b92 /src/mainboard/intel/tglrvp/variants
parente7881ed447c9a6ce5aea99f53c12f5c43fbd81dd (diff)
tigerlake mainboards: switch to devtree aliases for PMC MUX connectors
Now that soc_get_pmc_mux_device() is gone, the PMC MUX connector devices can be hooked up together via devicetree aliases. Signed-off-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Change-Id: Ib51764da5b3c029f9ac7ac60199a0aedfc7f29b1 Reviewed-on: https://review.coreboot.org/c/coreboot/+/45878 Reviewed-by: Furquan Shaikh <furquan@google.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb6
-rw-r--r--src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb6
2 files changed, 8 insertions, 4 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
index de93c99aa2..e16bd1f174 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb
@@ -306,6 +306,8 @@ chip soc/intel/tigerlake
end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end # eSPI 0xA080 - A09F
@@ -320,14 +322,14 @@ chip soc/intel/tigerlake
register "usb3_port_number" = "3"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 0 on end
+ device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "7"
register "usb3_port_number" = "4"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 1 on end
+ device generic 1 alias conn1 on end
end
end
end
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
index 4078894bfd..e6c0585787 100644
--- a/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
+++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up4/devicetree.cb
@@ -310,6 +310,8 @@ chip soc/intel/tigerlake
end # GSPI1 0xA0AB
device pci 1f.0 on
chip ec/google/chromeec
+ use conn0 as mux_conn[0]
+ use conn1 as mux_conn[1]
device pnp 0c09.0 on end
end
end # eSPI 0xA080 - A09F
@@ -324,14 +326,14 @@ chip soc/intel/tigerlake
register "usb3_port_number" = "3"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 0 on end
+ device generic 0 alias conn0 on end
end
chip drivers/intel/pmc_mux/conn
register "usb2_port_number" = "5"
register "usb3_port_number" = "2"
# SBU is fixed, HSL follows CC
register "sbu_orientation" = "TYPEC_ORIENTATION_NORMAL"
- device generic 1 on end
+ device generic 1 alias conn1 on end
end
end
end