diff options
| author | Felix Singer <felixsinger@posteo.net> | 2024-06-27 23:25:32 +0200 |
|---|---|---|
| committer | Felix Singer <felixsinger@posteo.net> | 2024-06-28 21:43:18 +0000 |
| commit | 8c1daf97519c64d4e0ac6c1ace3e54a2549a7612 (patch) | |
| tree | 5583478d3239621fe13f69b883e367fd0c2d1aa8 /src/mainboard/intel/tglrvp/variants | |
| parent | df141f61cc031c0b28385a36b4e636a4a3b32435 (diff) | |
tgl mainboards: Move SATA related settings into SATA device scope
Change-Id: I03508c50fe56fd85f8bf89f724863e546d4140e9
Signed-off-by: Felix Singer <felixsinger@posteo.net>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83249
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Matt DeVillier <matt.devillier@gmail.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 10 |
1 files changed, 5 insertions, 5 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index f03f67734c..7c60f0c9c3 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -59,10 +59,6 @@ chip soc/intel/tigerlake register "PcieClkSrcUsage[2]" = "0x3" register "PcieClkSrcUsage[3]" = "0x8" - register "SataSalpSupport" = "1" - register "SataPortsEnable[0]" = "1" - register "SataPortsEnable[1]" = "1" - # enabling EDP in PortA register "DdiPortAConfig" = "DDI_PORT_CFG_EDP" @@ -267,7 +263,11 @@ chip soc/intel/tigerlake device ref csme2 off end device ref heci3 off end device ref heci4 off end - device ref sata on end + device ref sata on + register "SataSalpSupport" = "1" + register "SataPortsEnable[0]" = "1" + register "SataPortsEnable[1]" = "1" + end device ref i2c4 off end device ref i2c5 on end device ref uart2 on end |