diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-12 01:08:14 -0700 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-15 12:53:33 +0000 |
| commit | 3663d55a23fb64ea88dd1fd18ae4b0ce29e71a61 (patch) | |
| tree | b648eab1c23d9f884253cf748bfbf65af2fdb918 /src/mainboard/intel/tglrvp/variants | |
| parent | 1f4f0b47f5f3a70658912eeca8172bc2f16b8351 (diff) | |
mb/intel/tglrvp: Enable CNVi in devicetree for Tiger Lake UP3
Enable CNVi in devicetree and add gpio pad configs for CNVi
BUG=none
BRANCH=none
TEST=Build and boot tglrvp
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: I71146960e0d53dae87946a0365dac6f224a72391
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39464
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Caveh Jalali <caveh@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb | 2 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c | 4 |
2 files changed, 5 insertions, 1 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb index 4492acb7ea..a43011f02c 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/devicetree.cb @@ -130,7 +130,7 @@ chip soc/intel/tigerlake device pci 0e.0 on end # VMD 0x9A0B # From PCH EDS(576591) - device pci 10.2 off end # CNVi: BT 0xA0F5 - A0F7 + device pci 10.2 on end # CNVi: BT 0xA0F5 - A0F7 device pci 10.6 off end # THC0 0xA0D0 device pci 10.7 off end # THC1 0xA0D1 device pci 12.0 off end # SensorHUB 0xA0FC diff --git a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c index b0c5bc1bd4..fa97a503b0 100644 --- a/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c +++ b/src/mainboard/intel/tglrvp/variants/tglrvp_up3/gpio.c @@ -61,6 +61,10 @@ static const struct pad_config gpio_table[] = { PAD_CFG_GPO(GPP_C5, 1, DEEP), PAD_CFG_GPI_APIC(GPP_C12, NONE, DEEP, EDGE_BOTH, INVERT), /* AUDIO JACK IRQ */ + /* CNVi */ + PAD_CFG_NF(GPP_F4, NONE, DEEP, NF1), /* CNV_RF_RST_L */ + PAD_CFG_NF(GPP_F5, NONE, DEEP, NF3), /* CNV_CLKREQ0 */ + }; /* Early pad configuration in bootblock */ |