diff options
| author | John Zhao <john.zhao@intel.com> | 2020-08-02 11:29:59 -0700 |
|---|---|---|
| committer | Tim Wawrzynczak <twawrzynczak@chromium.org> | 2020-08-12 19:43:07 +0000 |
| commit | 90883287b5db3c022bf45d98a00f88b4b9b7c055 (patch) | |
| tree | 00d1872fb9e9c80d0b66460fc9d823bd27e22a31 /src/mainboard/intel/tglrvp/variants/baseboard/include | |
| parent | 1d7ba15aa2e3a3ee9130101977405ef866bd7f79 (diff) | |
mb/intel/tglrvp: Add interrupt _CRS under CREC scope
Interrupt _CRS is missing under CREC scope. TGLRVP U/Y has GPP_A15
assigned to MECC_HPD2 as EC_SYNC_IRQ. Configure this GPP_A15 GPIO as
active low and level interruptible for EC sync interrupt configuration.
BUG=None
TEST=Booted to kernel and verified EC_SYNC_IRQ in the scope of CREC
current resource settings.
Signed-off-by: John Zhao <john.zhao@intel.com>
Change-Id: Idfe4d4e800866805ee8d758028ac7ddf4b259faa
Reviewed-on: https://review.coreboot.org/c/coreboot/+/44103
Reviewed-by: Vijay P Hiremath <vijay.p.hiremath@intel.com>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/variants/baseboard/include')
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h | 3 | ||||
| -rw-r--r-- | src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h | 3 |
2 files changed, 6 insertions, 0 deletions
diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h index c01829936d..4303faf0d2 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/ec.h @@ -56,6 +56,9 @@ /* Enable EC backed ALS device in ACPI */ #define EC_ENABLE_ALS_DEVICE +/* Enable EC sync interrupt, EC_SYNC_IRQ is defined in baseboard/gpio.h */ +#define EC_ENABLE_SYNC_IRQ + /* Enable EC backed PD MCU device in ACPI */ #define EC_ENABLE_PD_MCU_DEVICE diff --git a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h index de0adf6cff..b61276c0c1 100644 --- a/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h +++ b/src/mainboard/intel/tglrvp/variants/baseboard/include/baseboard/gpio.h @@ -12,4 +12,7 @@ /* EC wake is LAN_WAKE# which is a special DeepSX wake pin */ #define GPE_EC_WAKE GPE0_LAN_WAK +/* EC sync IRQ */ +#define EC_SYNC_IRQ GPP_A15_IRQ + #endif /* __BASEBOARD_GPIO_H__ */ |