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authorFurquan Shaikh <furquan@google.com>2020-12-31 21:15:34 -0800
committerPatrick Georgi <pgeorgi@google.com>2021-01-25 08:48:57 +0000
commitf06d046c1041477adbd6e40a038667a620641b38 (patch)
tree9f7a6905178a62d327094756c0d08ff73bb4fc7d /src/mainboard/intel/tglrvp/romstage_fsp_params.c
parent859ca18ced83ed3b8b529112da5f214ede3d38b0 (diff)
soc/intel/tgl and tgl mb/google,intel: Use the newly added meminit block driver
This change uses the newly added meminit block driver and updates TGL SoC and mainboard code accordingly. TEST=Verified that UPDs are configured correctly with and without this change. Change-Id: I6d58cd6568b7bbe03c4e3011b2301209893e85a9 Signed-off-by: Furquan Shaikh <furquan@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/49042 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org> Reviewed-by: EricR Lai <ericr_lai@compal.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/tglrvp/romstage_fsp_params.c')
-rw-r--r--src/mainboard/intel/tglrvp/romstage_fsp_params.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
index 47507f4eed..33415684ed 100644
--- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c
+++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c
@@ -42,14 +42,13 @@ void mainboard_memory_init_params(FSPM_UPD *mupd)
{
FSP_M_CONFIG *mem_cfg = &mupd->FspmConfig;
- const struct lpddr4x_cfg *mem_config = variant_memory_params();
- const struct spd_info spd_info = {
- .topology = MEMORY_DOWN,
- .md_spd_loc = SPD_CBFS,
+ const struct mb_cfg *mem_config = variant_memory_params();
+ const struct mem_spd spd_info = {
+ .topo = MEM_TOPO_MEMORY_DOWN,
.cbfs_index = mainboard_get_spd_index(),
};
bool half_populated = false;
- meminit_lpddr4x(mem_cfg, mem_config, &spd_info, half_populated);
+ memcfg_init(mem_cfg, mem_config, &spd_info, half_populated);
}