diff options
| author | Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com> | 2020-03-06 16:46:39 -0800 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2020-03-09 08:08:26 +0000 |
| commit | 9900cf80091ad1796c78c04b6ef6302410444480 (patch) | |
| tree | 9b67ea743db43287125b5635c0d85fafa2250645 /src/mainboard/intel/tglrvp/romstage_fsp_params.c | |
| parent | 7e303581bcda7d7a4a90d75a9b6f6698d55287ce (diff) | |
mb/intel/tglrvp: Add memory config for Tiger Lake UP4
Add LPDDR4 memory configuration for Tiger Lake UP4 platform which
includes
1. DQ/DQs Mapping
2. Board id Support
3. SPD indexing
BUG=none
BRANCH=none
TEST= Build TGL UP4 successfully
Signed-off-by: Srinidhi N Kaushik <srinidhi.n.kaushik@intel.com>
Change-Id: Ibbd7036919c1a91ef12049d2af657f0a3597b57e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/39365
Reviewed-by: Nick Vaccaro <nvaccaro@google.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/tglrvp/romstage_fsp_params.c')
| -rw-r--r-- | src/mainboard/intel/tglrvp/romstage_fsp_params.c | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/src/mainboard/intel/tglrvp/romstage_fsp_params.c b/src/mainboard/intel/tglrvp/romstage_fsp_params.c index 89ae0ab3fb..eb8fde0a6a 100644 --- a/src/mainboard/intel/tglrvp/romstage_fsp_params.c +++ b/src/mainboard/intel/tglrvp/romstage_fsp_params.c @@ -32,13 +32,16 @@ static uintptr_t mainboard_get_spd_index(void) printk(BIOS_INFO, "board id is 0x%x\n", board_id); switch (board_id) { - case TGL_U_LP4_MICRON: + case TGL_UP3_LP4_MICRON: + case TGL_UP4_LP4_MICRON: spd_index = SPD_ID_MICRON; break; - case TGL_U_LP4_SAMSUNG: + case TGL_UP3_LP4_SAMSUNG: + case TGL_UP4_LP4_SAMSUNG: spd_index = SPD_ID_SAMSUNG; break; - case TGL_U_LP4_HYNIX: + case TGL_UP3_LP4_HYNIX: + case TGL_UP4_LP4_HYNIX: spd_index = SPD_ID_HYNIX; break; default: |