mb/intel/tglrvp: Add initial mainboard code

This is a initial mainboard code aimed to serve as base for
further mainboard check-ins.

This is a copy patch from icelake_rvp as on commit ID:
I64db2460115f5fb35ca197b83440f8ee47470761

Below are the changes done over the copy patch:

 1. Rename "Icelake" with "Tigerlake".
 2. Replace "icelake_rvp" with "tglrvp".
 3. Rename "icl" with "tgl".
 4. Remove unwanted SPD file, add empty SPD as
    placeholder.
 5. Replace "soc/intel/icelake" with "soc/intel/tigerlake".
 6. Empty romstage_fsp_params.c, to fill it later with
    SOC specific config.
 7. Empty GPIO configuration, to be filled as per board.
 8. Change copyright year to 2019.
 9. Add board support namely BOARD_INTEL_TGLRVP_UP3
 10. Replace icl_u and icl_y variant with tglrvp variant.
 11. Remove basebord gpio.c and rely on variant override.
 12. Remove HDA verb table and config support.

Changes to follow on top of this:
 1. Add correct memory parameters, add SPDs.
 2. Clean up devicetree as per tigerlake SOC.
 3. Add GPIO support.
 4. Update chromeos.fmd to make 32MB BIOS region.
 5. clean up and make empty devicetree setting

TEST=Build tigerlake rvp board

Signed-off-by: Ravi Sarawadi <ravishankar.sarawadi@intel.com>
Change-Id: I86ada611de1cf28a1b872eea35cf41c0dc1c57f1
Reviewed-on: https://review.coreboot.org/c/coreboot/+/37868
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Wonkyu Kim <wonkyu.kim@intel.com>

1 files changed, 44 insertions, 0 deletions

diff --git a/src/mainboard/intel/tglrvp/chromeos.fmd b/src/mainboard/intel/tglrvp/chromeos.fmd
new file mode 100644
index 0000000000..bfbd304d36
--- /dev/null
+++ b/src/mainboard/intel/tglrvp/chromeos.fmd
@@ -0,0 +1,44 @@
+FLASH@0xfe000000 0x2000000 {
+	SI_ALL@0x0 0x1081000 {
+		SI_DESC@0x0 0x1000
+		SI_EC@0x1000 0x80000
+		SI_ME@0x81000 0x1000000
+	}
+	SI_BIOS@0x1400000 0xC00000 {
+		RW_SECTION_A@0x0 0x2d0000 {
+			VBLOCK_A@0x0 0x10000
+			FW_MAIN_A(CBFS)@0x10000 0x2bffc0
+			RW_FWID_A@0x2cffc0 0x40
+		}
+		RW_SECTION_B@0x2d0000 0x2d0000 {
+			VBLOCK_B@0x0 0x10000
+			FW_MAIN_B(CBFS)@0x10000 0x2bffc0
+			RW_FWID_B@0x2cffc0 0x40
+		}
+		RW_MISC@0x5a0000 0x30000 {
+			UNIFIED_MRC_CACHE@0x0 0x20000 {
+				RECOVERY_MRC_CACHE@0x0 0x10000
+				RW_MRC_CACHE@0x10000 0x10000
+			}
+			RW_ELOG@0x20000 0x4000
+			RW_SHARED@0x24000 0x4000 {
+				SHARED_DATA@0x0 0x2000
+				VBLOCK_DEV@0x2000 0x2000
+			}
+			RW_VPD@0x28000 0x2000
+			RW_NVRAM@0x2a000 0x6000
+		}
+		SMMSTORE@0x5d0000 0x40000
+		RW_LEGACY(CBFS)@0x610000 0x1c0000
+		WP_RO@0x7d0000 0x430000 {
+			RO_VPD@0x0 0x4000
+			RO_SECTION@0x4000 0x42c000 {
+				FMAP@0x0 0x800
+				RO_FRID@0x800 0x40
+				RO_FRID_PAD@0x840 0x7c0
+				GBB@0x1000 0xef000
+				COREBOOT(CBFS)@0xf0000 0x33c000
+			}
+		}
+	}
+}