diff options
| author | Shobhit Srivastava <shobhit.srivastava@intel.com> | 2015-08-10 11:48:23 +0530 |
|---|---|---|
| committer | Martin Roth <martinroth@google.com> | 2016-01-27 23:59:39 +0100 |
| commit | 97f09c3f191f3dad474d5c1fd56682001095703e (patch) | |
| tree | c30fa1d91c83eab05ed90ec9f64053822d9c07ae /src/mainboard/intel/strago/romstage.c | |
| parent | fc5489fc5e620adf3ec9f3d692444aa4c2b3801e (diff) | |
soc/braswell: Fix leakage on V1P8S rail
Tristate MMC1_RCLK pin to fix leakage on V1P8S rail.
Original-Reviewed-on: https://chromium-review.googlesource.com/292043
Original-Reviewed-by: Aaron Durbin <adurbin@chromium.org>
Original-Tested-by: Divagar Mohandass <divagar.mohandass@intel.com>
Change-Id: I76cc9211ba93b2596d3c0d772d99f8934656e01c
Signed-off-by: Shobhit Srivastava <shobhit.srivastava@intel.com>
Reviewed-on: https://review.coreboot.org/12730
Reviewed-by: Martin Roth <martinroth@google.com>
Tested-by: build bot (Jenkins)
Diffstat (limited to 'src/mainboard/intel/strago/romstage.c')
0 files changed, 0 insertions, 0 deletions