diff options
author | zaolin <zaolin.daisuki@gmail.com> | 2018-10-31 16:43:43 +0100 |
---|---|---|
committer | Nico Huber <nico.h@gmx.de> | 2018-11-19 15:43:37 +0000 |
commit | 3313a78e36da73f05da7402699f04909595a0c9d (patch) | |
tree | 1dcd09a9df05ec94d15178f929b7ae063fdf7646 /src/mainboard/intel/stargo2/romstage.c | |
parent | 0b8aefc6562c64665425617eddd22aec2610bda5 (diff) |
northbridge/intel/fsp_*: Remove legacy SoCs
* Remove FSP Sandy/Ivybrige which are unused.
* Open Source implementation isn't final but
good enough to replace FSP version.
* For new ports use NORTHBRIDGE_INTEL_IVYBRIDGE
and NORTHBRIDGE_INTEL_SANDYBRIDGE
Change-Id: I7b6bc4bfdd0481c8fe5b2b3d8f8b2eb9aa3c3b9e
Signed-off-by: Philipp Deppenwiese <zaolin.daisuki@gmail.com>
Reviewed-on: https://review.coreboot.org/29402
Reviewed-by: Nico Huber <nico.h@gmx.de>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/stargo2/romstage.c')
-rw-r--r-- | src/mainboard/intel/stargo2/romstage.c | 86 |
1 files changed, 0 insertions, 86 deletions
diff --git a/src/mainboard/intel/stargo2/romstage.c b/src/mainboard/intel/stargo2/romstage.c deleted file mode 100644 index 56f0fc0b4f..0000000000 --- a/src/mainboard/intel/stargo2/romstage.c +++ /dev/null @@ -1,86 +0,0 @@ -/* - * This file is part of the coreboot project. - * - * Copyright (C) 2007-2010 coresystems GmbH - * Copyright (C) 2011 The ChromiumOS Authors. All rights reserved. - * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC. - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License as published by - * the Free Software Foundation; version 2 of the License. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - */ - -#include <stdint.h> -#include <string.h> -#include <timestamp.h> -#include <arch/io.h> -#include <device/pci_def.h> -#include <device/pnp_def.h> -#include <cpu/x86/lapic.h> -#include <halt.h> -#include <reset.h> -#include <fsp_util.h> -#include <northbridge/intel/fsp_sandybridge/northbridge.h> -#include <northbridge/intel/fsp_sandybridge/raminit.h> -#include <southbridge/intel/fsp_i89xx/pch.h> -#include <southbridge/intel/fsp_i89xx/gpio.h> -#include <southbridge/intel/fsp_i89xx/me.h> -#include <southbridge/intel/fsp_i89xx/romstage.h> -#include <superio/winbond/wpcd376i/wpcd376i.h> -#include <superio/intel/i8900/i8900.h> -#include "gpio.h" - -#define SIO_PORT 0x2e -#define SERIAL_DEV PNP_DEV(SIO_PORT, 0x03) -#define WDT_DEV PNP_DEV(SIO_PORT, 0x06) -#define WDT_BASE_ADDR 0x600 - -/* - * Get function disables - any changes here should match in devicetree - * @param fd_mask - * @param fd2_mask - */ -void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask) -{ - *fd_mask |= PCH_DISABLE_ALWAYS; -} - -/** - * Get LPC setting - enables various devices (KB, mouse, etc.) - */ -uint16_t get_lpc_setting(void) -{ - /* Enable SuperIO (2E/4E) + COM1 & Keyboard controller */ - return CNF1_LPC_EN | CNF2_LPC_EN | COMA_LPC_EN | KBC_LPC_EN; -} - -/** - * /brief mainboard call for setup that needs to be done before fsp init - * - */ -void early_mainboard_romstage_entry(void) -{ - /* Early SuperIO setup - Using SIO Serial Port*/ - wpcd376i_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); - i8900_enable_wdt(WDT_DEV, WDT_BASE_ADDR); -} - -/** - * /brief mainboard call for setup that needs to be done after fsp init - * - */ -void late_mainboard_romstage_entry(void) -{ - -} - -void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer) -{ - /* No overrides needed */ - return; -} |