diff options
author | Marc Jones <marc.jones@se-eng.com> | 2015-09-15 23:05:00 -0600 |
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committer | Martin Roth <martinroth@google.com> | 2015-11-10 00:25:14 +0100 |
commit | 3b0a626edc9d1a45324fd8e77b10e4e49155bb8f (patch) | |
tree | 75a7a0fc8084031da63f3aa3e37448ecb7d5cb54 /src/mainboard/intel/stargo2/mainboard_smi.c | |
parent | 2d72345f80266555aa3c358d0b7bcda083687b5c (diff) |
mainboard/intel: Add Stargo2
The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.
Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/stargo2/mainboard_smi.c')
-rw-r--r-- | src/mainboard/intel/stargo2/mainboard_smi.c | 63 |
1 files changed, 63 insertions, 0 deletions
diff --git a/src/mainboard/intel/stargo2/mainboard_smi.c b/src/mainboard/intel/stargo2/mainboard_smi.c new file mode 100644 index 0000000000..b16b92f8a3 --- /dev/null +++ b/src/mainboard/intel/stargo2/mainboard_smi.c @@ -0,0 +1,63 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2008-2009 coresystems GmbH + * Copyright (C) 2013 Sage Electronic Engineering, LLC. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +#include <arch/io.h> +#include <console/console.h> +#include <cpu/x86/smm.h> +#include <southbridge/intel/fsp_i89xx/nvs.h> +#include <southbridge/intel/fsp_i89xx/pch.h> +#include <southbridge/intel/fsp_i89xx/me.h> +#include <northbridge/intel/fsp_sandybridge/sandybridge.h> +#include <cpu/intel/fsp_model_206ax/model_206ax.h> + +void mainboard_smi_sleep(u8 slp_typ) +{ + u8 reg8; + + switch (slp_typ) { + case SLP_TYP_S3: + case SLP_TYP_S4: + case SLP_TYP_S5: + break; + } +} + + +static int mainboard_finalized = 0; + +int mainboard_smi_apmc(u8 apmc) +{ + switch (apmc) { + case APM_CNT_FINALIZE: + if (mainboard_finalized) { + printk(BIOS_DEBUG, "SMI#: Already finalized\n"); + return 0; + } + + intel_me_finalize_smm(); + intel_pch_finalize_smm(); + intel_sandybridge_finalize_smm(); + intel_model_206ax_finalize_smm(); + + mainboard_finalized = 1; + break; + } + return 0; +} |