mainboard/intel: Add Stargo2

The Intel Stargo2 is a communications device reference design.
This mainboard uses the Sandy/Ivy Bridge and is paired with
the i89xx southbridge. The FSP package is available from Intel:
https://intel.com/fsp.

Change-Id: I75c527f0eb0de1ee6ac13d8d276d7cf23b5b120c
Signed-off-by: Marc Jones <marc.jones@se-eng.com>
Reviewed-on: http://review.coreboot.org/12170
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>

1 files changed, 97 insertions, 0 deletions

diff --git a/src/mainboard/intel/stargo2/devicetree.cb b/src/mainboard/intel/stargo2/devicetree.cb
new file mode 100644
index 0000000000..5cf8384ec1
--- /dev/null
+++ b/src/mainboard/intel/stargo2/devicetree.cb
@@ -0,0 +1,97 @@
+chip northbridge/intel/fsp_sandybridge
+
+	device cpu_cluster 0 on
+		chip cpu/intel/socket_BGA1284
+			device lapic 0 on end
+		end
+		chip cpu/intel/fsp_model_206ax
+			# Magic APIC ID to locate this chip
+			device lapic 0xACAC off end
+
+			register "c1_battery" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_battery" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_battery" = "5"	# ACPI(C3) = MWAIT(C7)
+
+			register "c1_acpower" = "3"	# ACPI(C1) = MWAIT(C3)
+			register "c2_acpower" = "4"	# ACPI(C2) = MWAIT(C6)
+			register "c3_acpower" = "5"	# ACPI(C3) = MWAIT(C7)
+		end
+	end
+
+	device domain 0 on
+		device pci 00.0 on end # host bridge
+		device pci 01.0 on end # host bridge (slot 2 - black x16 slot (only x8))
+		device pci 01.1 on end # host bridge (PCIe Ethernet controllers)
+		device pci 01.2 off end # host bridge (off - no additional bifurcation)
+		device pci 02.0 off end # vga controller
+		device pci 06.0 on end # host bridge (slot 1 - blue x4 slot)
+
+		chip southbridge/intel/fsp_i89xx # Intel Series 89xx Cave Creek PCH
+			register "ide_legacy_combined" = "0x0"
+			register "sata_ahci" = "0x01"
+			register "sata_port_map" = "0x30"
+			register "c2_latency" = "1"
+			register "p_cnt_throttling_supported" = "0"
+
+			device pci 16.0 on end # Management Engine Interface 1
+			device pci 16.1 off end # Management Engine Interface 2
+			device pci 16.2 off end # Management Engine IDE-R
+			device pci 16.3 off end # Management Engine KT
+			device pci 1c.0 on end # PCIe Port #1 (Slot #3 - x1)
+			device pci 1c.1 on end # PCIe Port #2 (Slot #4 - x1)
+			device pci 1c.2 on end # PCIe Port #3 (Slot #5 - x1)
+			device pci 1c.3 on end # PCIe Port #4 (Slot #6 - x1)
+			device pci 1d.0 on end # USB2 EHCI #1
+			device pci 1f.0 on # LPC bridge
+
+				# The top serial port is controlled by jumper
+				# J3a3.  If the jumper is off, the serial
+				# port connector is routed to the SIO.  If
+				# the jumper is on, the connector goes to
+				# the PCH's serial port.  There is no way
+				# to tell in software which it's connected
+				# to.
+
+				chip superio/intel/i8900
+					device pnp 4e.4 on  #  Com3
+						io 0x60 = 0x3E8
+						irq 0x70 = 4
+					end
+					device pnp 4e.5 on  #  Com2
+						io 0x60 = 0x2f8
+						irq 0x70 = 3
+					end
+					device pnp 4e.6 on  #  Watchdog Timer
+						io 0x60 = 0x600
+						irq 0x70 = 7
+					end
+				end
+
+				chip superio/winbond/wpcd376i
+					device pnp 2e.0 off end # FDC
+					device pnp 2e.1 off end # LPT
+					device pnp 2e.2 off end # IR
+					device pnp 2e.3 on      # Com1
+						io 0x60 = 0x3f8
+						irq 0x70 = 4
+					end
+					device pnp 2e.4 off end # System wakeup
+					device pnp 2e.5 on      # PS/2 mouse
+						irq 0x70 = 0x0C
+					end
+					device pnp 2e.6 on      # PS/2 keyboard
+						io 0x60 = 0x60
+						io 0x62 = 0x64
+						irq 0x70 = 0x01
+					end
+					device pnp 2e.7 off end # GPIO
+				end
+			end
+			device pci 1f.2 on end # SATA Controller 1
+			device pci 1f.3 on end # SMBus
+			device pci 1f.5 off end # SATA Controller 2
+			device pci 1f.6 on end # Thermal
+			device pci 1f.7 on end # WDT
+		end
+	end
+end