diff options
| author | Lee Leahy <leroy.p.leahy@intel.com> | 2015-05-12 18:25:25 -0700 |
|---|---|---|
| committer | Leroy P Leahy <leroy.p.leahy@intel.com> | 2015-07-17 20:19:29 +0200 |
| commit | 01464a69b8ceaee0e145fcbe61a99e0a077a2332 (patch) | |
| tree | 9c7796ce7020a2c0e719442460cd135471d36261 /src/mainboard/intel/sklrvp/dsdt.asl | |
| parent | 5cb9ddad3e8d487945c4a1e4b82575369b08be52 (diff) | |
mainboard/intel: Add Skylake based RVP3 board
Initial files to support the Intel Skylake RVP3
Matches chromium tree at 927026db
This board uses the Skylake FSP 1.1 image and does not build without the
FspUpdVpd.h file.
BRANCH=none
BUG=None
TEST=Build and run on sklrvp
Change-Id: I5e7fff8f62a737e627e25c1e03e343d6167041ea
Signed-off-by: Lee Leahy <leroy.p.leahy@intel.com>
Reviewed-on: http://review.coreboot.org/10343
Tested-by: build bot (Jenkins)
Reviewed-by: Stefan Reinauer <stefan.reinauer@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/sklrvp/dsdt.asl')
| -rw-r--r-- | src/mainboard/intel/sklrvp/dsdt.asl | 53 |
1 files changed, 53 insertions, 0 deletions
diff --git a/src/mainboard/intel/sklrvp/dsdt.asl b/src/mainboard/intel/sklrvp/dsdt.asl new file mode 100644 index 0000000000..8a8164ad84 --- /dev/null +++ b/src/mainboard/intel/sklrvp/dsdt.asl @@ -0,0 +1,53 @@ +/* + * This file is part of the coreboot project. + * + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2015 Intel Corporation. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; version 2 of the License. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc. + */ + +DefinitionBlock( + "dsdt.aml", + "DSDT", + 0x02, // DSDT revision: ACPI v2.0 + "COREv4", // OEM id + "COREBOOT", // OEM table id + 0x20110725 // OEM revision +) +{ + // Some generic macros + #include <soc/intel/skylake/acpi/platform.asl> + + // global NVS and variables + #include <soc/intel/skylake/acpi/globalnvs.asl> + + // CPU + #include <soc/intel/skylake/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/skylake/acpi/systemagent.asl> + #include <soc/intel/skylake/acpi/pch.asl> + } + } + + // Chipset specific sleep states + #include <soc/intel/skylake/acpi/sleepstates.asl> + + // Mainboard specific + #include "acpi/mainboard.asl" +} |