diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-01-20 08:00:26 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-02-11 07:43:16 +0000 |
| commit | 2151f7561d728a9280d69d20ef56a9fe44db7cb1 (patch) | |
| tree | 65fb6578e96190c39f1a43c4936df8b99e3aeb9d /src/mainboard/intel/shadowmountain | |
| parent | a90854d429c5775d51021fbd488c9a2af153f250 (diff) | |
mb/intel/shadowmountain: Add the ASL code
This patch includes the DSDT ASL code for shadowmountain board.
BUG=b:175808146
TEST= Boot shadowmountain board, dump and verify the DSDT ASL entries.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: I511b2d23c424b0565ad1abcc3b41cace1b89936e
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49733
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/dsdt.asl | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/dsdt.asl b/src/mainboard/intel/shadowmountain/dsdt.asl index c8dc9ee2c3..f94ad378c9 100644 --- a/src/mainboard/intel/shadowmountain/dsdt.asl +++ b/src/mainboard/intel/shadowmountain/dsdt.asl @@ -1,6 +1,8 @@ /* SPDX-License-Identifier: GPL-2.0-or-later */ #include <acpi/acpi.h> +#include <baseboard/ec.h> +#include <baseboard/gpio.h> DefinitionBlock( "dsdt.aml", @@ -12,4 +14,31 @@ DefinitionBlock( ) { #include <acpi/dsdt_top.asl> + #include <soc/intel/common/block/acpi/acpi/platform.asl> + + /* global NVS and variables */ + #include <soc/intel/common/block/acpi/acpi/globalnvs.asl> + + /* CPU */ + #include <cpu/intel/common/acpi/cpu.asl> + + Scope (\_SB) { + Device (PCI0) + { + #include <soc/intel/common/block/acpi/acpi/northbridge.asl> + #include <soc/intel/alderlake/acpi/southbridge.asl> + #include <soc/intel/alderlake/acpi/tcss.asl> + } + } + + /* Chrome OS Embedded Controller */ + Scope (\_SB.PCI0.LPCB) + { + // ACPI code for EC SuperIO functions + #include <ec/google/chromeec/acpi/superio.asl> + // ACPI code for EC functions + #include <ec/google/chromeec/acpi/ec.asl> + } + + #include <southbridge/intel/common/acpi/sleepstates.asl> } |