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| author | Felix Held <felix-coreboot@felixheld.de> | 2024-08-06 18:12:37 +0200 |
|---|---|---|
| committer | Felix Held <felix-coreboot@felixheld.de> | 2024-08-07 16:31:35 +0000 |
| commit | 35946f957affc2e23830750dbf2a26586093ca76 (patch) | |
| tree | 0f74cd709d8ac1874c6278167706235fd1194032 /src/mainboard/intel/shadowmountain | |
| parent | c3245274e960670fc7092a6676e3fb95ca8ea7fd (diff) | |
soc/amd/common/include/spi: add and use SPI_MISC_CNTRL define
This register is currently used by the SPI DMA code that sets an
undocumented bit. A later patch will add and use some other bit in this
register.
Signed-off-by: Felix Held <felix-coreboot@felixheld.de>
Change-Id: I48447dcfb3cee07619a9b42434731f0b21458021
Reviewed-on: https://review.coreboot.org/c/coreboot/+/83773
Reviewed-by: Matt DeVillier <matt.devillier@amd.corp-partner.google.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain')
0 files changed, 0 insertions, 0 deletions