diff options
author | V Sowmya <v.sowmya@intel.com> | 2021-01-20 07:15:37 +0530 |
---|---|---|
committer | Subrata Banik <subrata.banik@intel.com> | 2021-02-22 05:46:58 +0000 |
commit | 738aaa24d38385b9ba8078d452dbaa4f36cdf4e6 (patch) | |
tree | 99d3fd3ac9567dc4325a3a4b9e41259adf610b9f /src/mainboard/intel/shadowmountain/romstage.c | |
parent | 43f6598b2781bd087a99626967a5186ecc2b9163 (diff) |
mb/intel/shadowmountain: Add the romstage code
This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/romstage.c')
-rw-r--r-- | src/mainboard/intel/shadowmountain/romstage.c | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/romstage.c b/src/mainboard/intel/shadowmountain/romstage.c new file mode 100644 index 0000000000..1e29e8029d --- /dev/null +++ b/src/mainboard/intel/shadowmountain/romstage.c @@ -0,0 +1,23 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ +#include <assert.h> +#include <console/console.h> +#include <fsp/api.h> +#include <soc/romstage.h> +#include <spd_bin.h> +#include <string.h> +#include <soc/meminit.h> +#include <baseboard/variants.h> +#include <cbfs.h> + +void mainboard_memory_init_params(FSPM_UPD *mupd) +{ + const struct mb_cfg *mem_config = variant_memory_params(); + const bool half_populated = false; + + const struct mem_spd lp5_spd_info = { + .topo = MEM_TOPO_MEMORY_DOWN, + .cbfs_index = variant_memory_sku(), + }; + + memcfg_init(&mupd->FspmConfig, mem_config, &lp5_spd_info, half_populated); +} |