diff options
| author | V Sowmya <v.sowmya@intel.com> | 2021-01-20 07:15:37 +0530 |
|---|---|---|
| committer | Subrata Banik <subrata.banik@intel.com> | 2021-02-22 05:46:58 +0000 |
| commit | 738aaa24d38385b9ba8078d452dbaa4f36cdf4e6 (patch) | |
| tree | 99d3fd3ac9567dc4325a3a4b9e41259adf610b9f /src/mainboard/intel/shadowmountain/Kconfig | |
| parent | 43f6598b2781bd087a99626967a5186ecc2b9163 (diff) | |
mb/intel/shadowmountain: Add the romstage code
This patch includes the romstage changes for the
shadowmountain board.
BUG=b:175808146
TEST= Build and boot shadowmountain board till early ramstage.
Signed-off-by: V Sowmya <v.sowmya@intel.com>
Change-Id: Ifd0bbcea9d4916d82bb1e3c275dd79d97a79727a
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49731
Reviewed-by: Subrata Banik <subrata.banik@intel.com>
Reviewed-by: Aamir Bohra <aamir.bohra@intel.com>
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/shadowmountain/Kconfig')
| -rw-r--r-- | src/mainboard/intel/shadowmountain/Kconfig | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/shadowmountain/Kconfig b/src/mainboard/intel/shadowmountain/Kconfig index 66ae63672e..9c8d044ca9 100644 --- a/src/mainboard/intel/shadowmountain/Kconfig +++ b/src/mainboard/intel/shadowmountain/Kconfig @@ -15,6 +15,7 @@ config BOARD_SPECIFIC_OPTIONS select EC_GOOGLE_CHROMEEC_LPC select HAVE_ACPI_RESUME select HAVE_ACPI_TABLES + select HAVE_SPD_IN_CBFS select INTEL_LPSS_UART_FOR_CONSOLE select MAINBOARD_HAS_CHROMEOS select SOC_INTEL_ALDERLAKE |