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| author | Michael Niewöhner <foss@mniewoehner.de> | 2020-12-21 17:09:08 +0100 |
|---|---|---|
| committer | Michael Niewöhner <foss@mniewoehner.de> | 2021-01-21 18:13:19 +0000 |
| commit | f31c2f2b7a27fbb2d8a26125f3d1852c821ea0b7 (patch) | |
| tree | c4119fd83ea21d42d056a3ce8bc89d78b1de87a0 /src/mainboard/intel/saddlebrook | |
| parent | 17721be11a64b82d1d2bb4165bd3bf8380016fdf (diff) | |
mb/up/squared: do LPC/eSPI pad configuration at board-level
Do LPC/eSPI pad configuration at board-level to match other platforms by
adding an appropriate early gpio table in the bootblock.
The soc code gets dropped in CB:49410.
Change-Id: If0693a4419c58dde3c4536698940f03c30304b9d
Signed-off-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/49414
Reviewed-by: Angel Pons <th3fanbus@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
0 files changed, 0 insertions, 0 deletions