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| author | Arthur Heymans <arthur@aheymans.xyz> | 2019-05-23 14:41:19 +0200 |
|---|---|---|
| committer | Patrick Georgi <pgeorgi@google.com> | 2019-05-29 20:17:48 +0000 |
| commit | 73ac12196c61c8d0c21a54dfa87b858662d6859a (patch) | |
| tree | 225d0510e4df457989fd6add4d994354930af4e7 /src/mainboard/intel/saddlebrook | |
| parent | 1ac5ecbfd1acf79f3bea288ef644c28ba54cc685 (diff) | |
drivers/intel/fsp1.1: Simplify bootflow and clean up
This gets rid of the boilerplate back and forward calls between the
SOC/FSP-driver code and mainboard code.
Change-Id: I5d4a10d1da6b3ac5e65efd7f82607b56b80e08d4
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/32961
Reviewed-by: Patrick Georgi <pgeorgi@google.com>
Reviewed-by: Frans Hendriks <fhendriks@eltan.com>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/romstage.c | 6 |
1 files changed, 0 insertions, 6 deletions
diff --git a/src/mainboard/intel/saddlebrook/romstage.c b/src/mainboard/intel/saddlebrook/romstage.c index 48d39db309..82b85fd700 100644 --- a/src/mainboard/intel/saddlebrook/romstage.c +++ b/src/mainboard/intel/saddlebrook/romstage.c @@ -33,12 +33,6 @@ void car_mainboard_pre_console_init(void) nuvoton_enable_serial(SERIAL_DEV, CONFIG_TTYS0_BASE); } -void mainboard_romstage_entry(struct romstage_params *params) -{ - post_code(0x31); - romstage_common(params); -} - void mainboard_memory_init_params( struct romstage_params *params, MEMORY_INIT_UPD *memory_params) |