diff options
| author | Angel Pons <th3fanbus@gmail.com> | 2021-02-20 00:16:47 +0100 |
|---|---|---|
| committer | Angel Pons <th3fanbus@gmail.com> | 2021-03-01 19:37:36 +0000 |
| commit | 6bd99f9ada29f199f9bf50f1cd6b37e24ee1eb7b (patch) | |
| tree | 951dd60f3e563bfbbc3c33c2f9c0fd4e1331e981 /src/mainboard/intel/saddlebrook/devicetree.cb | |
| parent | ba4cfb504ca1e8246d1ea135dfb566c3db5835cb (diff) | |
soc/intel/skylake: Clean up SD GPIO handling
This is to align with newer platforms.
Change-Id: If33ea3a7835ec071be3fd060f9712c47678bd6bf
Signed-off-by: Angel Pons <th3fanbus@gmail.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/50963
Reviewed-by: Michael Niewöhner <foss@mniewoehner.de>
Reviewed-by: Tim Wawrzynczak <twawrzynczak@chromium.org>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Diffstat (limited to 'src/mainboard/intel/saddlebrook/devicetree.cb')
| -rw-r--r-- | src/mainboard/intel/saddlebrook/devicetree.cb | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/mainboard/intel/saddlebrook/devicetree.cb b/src/mainboard/intel/saddlebrook/devicetree.cb index 0da097fa4a..d049db17a2 100644 --- a/src/mainboard/intel/saddlebrook/devicetree.cb +++ b/src/mainboard/intel/saddlebrook/devicetree.cb @@ -197,7 +197,7 @@ chip soc/intel/skylake register "SendVrMbxCmd" = "2" # Use default SD card detect GPIO configuration - #register "sdcard_cd_gpio_default" = "GPP_A7" + #register "sdcard_cd_gpio" = "GPP_A7" device cpu_cluster 0 on device lapic 0 on end |