diff options
| author | Usha P <usha.p@intel.com> | 2023-01-16 15:03:13 +0530 |
|---|---|---|
| committer | Eric Lai <eric_lai@quanta.corp-partner.google.com> | 2023-02-15 02:10:12 +0000 |
| commit | df6bc335f51bc2016da6421019f5c85e6e597206 (patch) | |
| tree | ba4930777967116254238570640dcf981ac61622 /src/mainboard/intel/mtlrvp | |
| parent | f8665f08faaed99e81fd14bc10c970ab95ecd133 (diff) | |
mb/intel/mtlrvp: Enable S0ix
This patch enables S0ix for MTL-P RVP platform
BUG=None
TEST=Able to enter low power idle S0 on MTL-P RVP
Signed-off-by: Usha P <usha.p@intel.com>
Change-Id: Id84f21d81197e44d6dd0dd8888c80848aa3679e0
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/71994
Reviewed-by: Meera Ravindranath <meera.ravindranath@intel.com>
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Reviewed-by: Harsha B R <harsha.b.r@intel.com>
Reviewed-by: Krishna P Bhat D <krishna.p.bhat.d@intel.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 3 |
1 files changed, 3 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index b69fddd186..e7ad2e8e03 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -39,6 +39,9 @@ chip soc/intel/meteorlake # Enable CNVi BT register "cnvi_bt_core" = "true" + # Enable S0ix + register "s0ix_enable" = "1" + # Enable EDP in PortA register "ddi_port_A_config" = "1" # Enable HDMI in Port B |