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authorSubrata Banik <subratabanik@google.com>2023-11-16 19:24:52 +0000
committerFelix Held <felix-coreboot@felixheld.de>2023-11-21 13:40:34 +0000
commit5578d912576a518175c8067b0ad88961b9032660 (patch)
treeb61a70a0ab235ca9f5ea8bbb8c1e24b71ce2b396 /src/mainboard/intel/mtlrvp
parent3d9a26e7a9da4bcb3832da7c3da100a68dcc5872 (diff)
mb/{google,intel}/{rex,mtlrvp}: Enable SOC_INTEL_COMMON_BASECODE_RAMTOP
This patch enables the `SOC_INTEL_COMMON_BASECODE_RAMTOP` config option for select mainboards, as not all board variants may want to enable this config due to underlying SoC dependencies. Mainboards that attempt to enable early caching have exhibited soft hangs while switching between pre-RAM and post-RAM phases. This patch allows mainboards to choose to enable this option without enabling it by default (which could cause boot hangs). Furthermore, it reorganizes the configuration options under BOARD_GOOGLE_BASEBOARD_REX in alphabetical order for better readability. BUG=b:306677879 TEST=Enable SOC_INTEL_COMMON_BASECODE_RAMTOP for google/rex and intel/mtlrvp. Change-Id: If380c2ecbee4f6437c3d58bfb55be076a4902997 Signed-off-by: Subrata Banik <subratabanik@google.com> Reviewed-on: https://review.coreboot.org/c/coreboot/+/79048 Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Kapil Porwal <kapilporwal@google.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp')
-rw-r--r--src/mainboard/intel/mtlrvp/Kconfig1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/Kconfig b/src/mainboard/intel/mtlrvp/Kconfig
index 26faf91d3f..b541b76146 100644
--- a/src/mainboard/intel/mtlrvp/Kconfig
+++ b/src/mainboard/intel/mtlrvp/Kconfig
@@ -17,6 +17,7 @@ config BOARD_INTEL_MTLRVP_COMMON
select HAVE_ACPI_TABLES
select HAVE_SPD_IN_CBFS
select MAINBOARD_HAS_CHROMEOS
+ select SOC_INTEL_COMMON_BASECODE_RAMTOP
select SOC_INTEL_COMMON_BLOCK_VARIANT_POWER_LIMIT
select SOC_INTEL_CSE_LITE_SKU
select SOC_INTEL_METEORLAKE_U_H