diff options
| author | Harsha B R <harsha.b.r@intel.com> | 2023-02-01 10:47:20 +0530 |
|---|---|---|
| committer | Paul Fagerburg <pfagerburg@chromium.org> | 2023-02-04 01:41:59 +0000 |
| commit | 48f0b1142be736b7a2d878a2a8371bafa780c7e0 (patch) | |
| tree | b6da3bb99107a2e3cc56ce8508e6117926c7f90b /src/mainboard/intel/mtlrvp | |
| parent | ab7b892ad1c0d1dee468b6d6ff3b9229a33bcbe5 (diff) | |
mb/intel/mtlrvp: Enable CNVi BT Core and Wifi
This patch enables CNVi_BT Core and Wifi for mtlrvp based on mtlrvp
schematics.
1. Enable CNVi BT Core in device tree
2. Enable CNVi Wifi (pci 14.3) device in device tree
BUG=b:224325352
BRANCH=None
TEST=Able to observe corresponding UPD configuration with FSP dump and
able to boot mtlrvp (LP5/DDR5) to ChromeOS.
CNVi Mode = 1
Wi-Fi Core = 1
BT Core = 1
BT Audio Offload = 0
BT Interface = 1
Signed-off-by: Harsha B R <harsha.b.r@intel.com>
Change-Id: I22575bf31b540f9dc1149a2766268285001b72f4
Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/72695
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp')
| -rw-r--r-- | src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb | 12 |
1 files changed, 12 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb index 8cdbeea5a8..15cdee1504 100644 --- a/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb +++ b/src/mainboard/intel/mtlrvp/variants/baseboard/mtlrvp_p/devicetree.cb @@ -36,6 +36,9 @@ chip soc/intel/meteorlake register "tcss_ports[2]" = "TCSS_PORT_DEFAULT(OC0)" register "tcss_ports[3]" = "TCSS_PORT_DEFAULT(OC0)" + # Enable CNVi BT + register "cnvi_bt_core" = "true" + device domain 0 on device ref igpu on end device ref heci1 on end @@ -63,6 +66,15 @@ chip soc/intel/meteorlake }" end # PCIE11 SSD Gen4 device ref xhci on end + + device ref cnvi_wifi on + chip drivers/wifi/generic + register "wake" = "GPE0_PME_B0" + register "enable_cnvi_ddr_rfim" = "true" + device generic 0 on end + end + end + device ref i2c0 on end device ref i2c1 on end device ref i2c2 on end |