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authorJamie Ryu <jamie.m.ryu@intel.com>2022-07-22 12:03:53 -0700
committerEric Lai <eric_lai@quanta.corp-partner.google.com>2022-11-08 00:26:17 +0000
commit4d23b9f18b020aa266ee9b4eac5898803cd4f2fd (patch)
treedc954c1a84f371a5d19cc9e09e1ba3e722c21802 /src/mainboard/intel/mtlrvp/dsdt.asl
parentd92745bb989816f17c714e6db4304dd10d931c85 (diff)
mb/intel/mtlrvp: Enable ACPI and add ACPI table
This enables ACPI configuration and add ACPI table. BUG=b:224325352 TEST=util/abuild/abuild -p none -t intel/mtlrvp -a -c max Signed-off-by: Jamie Ryu <jamie.m.ryu@intel.com> Change-Id: I8264197fd0acdd7e19b9a36fb22822447b013202 Reviewed-on: https://review.coreboot.org/c/coreboot/+/66100 Reviewed-by: Nick Vaccaro <nvaccaro@google.com> Reviewed-by: Subrata Banik <subratabanik@google.com> Reviewed-by: Angel Pons <th3fanbus@gmail.com> Tested-by: build bot (Jenkins) <no-reply@coreboot.org> Reviewed-by: Usha P <usha.p@intel.com> Reviewed-by: Eric Lai <eric_lai@quanta.corp-partner.google.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp/dsdt.asl')
-rw-r--r--src/mainboard/intel/mtlrvp/dsdt.asl14
1 files changed, 14 insertions, 0 deletions
diff --git a/src/mainboard/intel/mtlrvp/dsdt.asl b/src/mainboard/intel/mtlrvp/dsdt.asl
index 82d11c67fb..f5728a66b7 100644
--- a/src/mainboard/intel/mtlrvp/dsdt.asl
+++ b/src/mainboard/intel/mtlrvp/dsdt.asl
@@ -11,4 +11,18 @@ DefinitionBlock(
0x20110725
)
{
+ #include <acpi/dsdt_top.asl>
+ #include <cpu/intel/common/acpi/cpu.asl>
+ #include <soc/intel/common/block/acpi/acpi/globalnvs.asl>
+ #include <soc/intel/common/block/acpi/acpi/platform.asl>
+
+ Scope (\_SB) {
+ Device (PCI0)
+ {
+ #include <soc/intel/common/block/acpi/acpi/northbridge.asl>
+ #include <soc/intel/meteorlake/acpi/southbridge.asl>
+ }
+ }
+
+ #include <southbridge/intel/common/acpi/sleepstates.asl>
}