diff options
| author | Rui Zhou <zhourui@huaqin.corp-partner.google.com> | 2024-11-20 11:13:04 +0800 |
|---|---|---|
| committer | Subrata Banik <subratabanik@google.com> | 2024-11-21 06:16:00 +0000 |
| commit | 7564a0c57cfcb68c652a35444aa457fc94efe283 (patch) | |
| tree | 72410f48c78dcee02453b53e6d145e48a1ea2ace /src/mainboard/intel/mtlrvp/bootblock.c | |
| parent | a12c8de14b7a62e60c061c44846467aa4b782c6c (diff) | |
mb/google/nissa/var/rull: add RAM ID MT62F1G32D2DS-023 WT:B
Add RAM ID for DDR MICRON MT62F1G32D2DS-023 WT:B
BUG=b:378821948
BRANCH=None
TEST=boot to kernel success
Change-Id: I22e00cffaf6007c64d0c9ffa5f5dde528e3d8952
Signed-off-by: Rui Zhou <zhourui@huaqin.corp-partner.google.com>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/85202
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Subrata Banik <subratabanik@google.com>
Reviewed-by: Lei Cao <caolei6@huaqin.corp-partner.google.com>
Reviewed-by: Eric Lai <ericllai@google.com>
Diffstat (limited to 'src/mainboard/intel/mtlrvp/bootblock.c')
0 files changed, 0 insertions, 0 deletions