diff options
| author | Martin Roth <martin.roth@se-eng.com> | 2014-11-16 17:09:15 -0700 |
|---|---|---|
| committer | Martin Roth <gaumless@gmail.com> | 2014-11-19 03:56:38 +0100 |
| commit | e55a7c540311ee7bb1701b8bbe546b490c3c6d55 (patch) | |
| tree | ae45849e5815f56d0d5c242db797bff60539a0af /src/mainboard/intel/minnowmax | |
| parent | cd31afdc3cb3a83639e09111e6e9ed8bbca9326e (diff) | |
fsp_baytrail: Update chip.h UPD entries to match names in fspvpd.h
The entries in chip.h are used to set the UPD values. These had
originally been shortened and did not match the names of the structure
entries in vendorcode/intel/fsp/baytrail/include/fspvpd.h
This patch aligns the names.
- Update names in chip.h.
- Update names in devictree registers for bayley bay and minnow max.
- Update names in chipset_fsp_util.c
Change-Id: I8d7e34195cec2e63802d7e07e5aed71735556936
Signed-off-by: Martin Roth <martin.roth@se-eng.com>
Reviewed-on: http://review.coreboot.org/7486
Reviewed-by: Paul Menzel <paulepanter@users.sourceforge.net>
Reviewed-by: FEI WANG <wangfei.jimei@gmail.com>
Tested-by: build bot (Jenkins)
Reviewed-by: Edward O'Callaghan <eocallaghan@alterapraxis.com>
Diffstat (limited to 'src/mainboard/intel/minnowmax')
| -rw-r--r-- | src/mainboard/intel/minnowmax/devicetree.cb | 20 |
1 files changed, 10 insertions, 10 deletions
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb index a0ac7ae74a..dd999a09e0 100644 --- a/src/mainboard/intel/minnowmax/devicetree.cb +++ b/src/mainboard/intel/minnowmax/devicetree.cb @@ -24,16 +24,16 @@ chip soc/intel/fsp_baytrail register "fadt_boot_arch" = "ACPI_FADT_LEGACY_FREE" #### FSP register settings #### - register "SataMode" = "SATA_MODE_AHCI" - register "MrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" - register "MrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" - register "MrcInitTsegSize" = "TSEG_SIZE_8_MB" - register "MrcInitMmioSize" = "MMIO_SIZE_DEFAULT" - register "eMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" - register "IgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" - register "ApertureSize" = "APERTURE_SIZE_DEFAULT" - register "GttSize" = "GTT_SIZE_DEFAULT" - register "LpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" + register "PcdSataMode" = "SATA_MODE_AHCI" + register "PcdMrcInitSPDAddr1" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitSPDAddr2" = "SPD_ADDR_DEFAULT" + register "PcdMrcInitTsegSize" = "TSEG_SIZE_8_MB" + register "PcdMrcInitMmioSize" = "MMIO_SIZE_DEFAULT" + register "PcdeMMCBootMode" = "EMMC_FOLLOWS_DEVICETREE" + register "PcdIgdDvmt50PreAlloc" = "IGD_MEMSIZE_DEFAULT" + register "PcdApertureSize" = "APERTURE_SIZE_DEFAULT" + register "PcdGttSize" = "GTT_SIZE_DEFAULT" + register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT" register "AzaliaAutoEnable" = "AZALIA_FOLLOWS_DEVICETREE" register "LpeAcpiModeEnable" = "LPE_ACPI_MODE_DISABLED" |