mb/*/*: Drop FSP_BAYTRAIL support

Relocatable ramstage, postcar stage and C_ENVIRONMENT_BOOTBLOCK are
now mandatory features, which this platform lacks.

Change-Id: I08c21fd7e5cf8996911c3912bdbaf12d6450db42
Signed-off-by: Arthur Heymans <arthur@aheymans.xyz>
Reviewed-on: https://review.coreboot.org/c/coreboot/+/36981
Tested-by: build bot (Jenkins) <no-reply@coreboot.org>
Reviewed-by: Kyösti Mälkki <kyosti.malkki@gmail.com>
Reviewed-by: HAOUAS Elyes <ehaouas@noos.fr>
Reviewed-by: David Hendricks <david.hendricks@gmail.com>
Reviewed-by: Werner Zeh <werner.zeh@siemens.com>

17 files changed, 0 insertions, 953 deletions

diff --git a/src/mainboard/intel/minnowmax/Kconfig b/src/mainboard/intel/minnowmax/Kconfig
deleted file mode 100644
index ca24c92aa6..0000000000
--- a/src/mainboard/intel/minnowmax/Kconfig
+++ /dev/null
@@ -1,64 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-if BOARD_INTEL_MINNOWMAX
-
-config BOARD_SPECIFIC_OPTIONS
-	def_bool y
-	select SOC_INTEL_FSP_BAYTRAIL
-	select BOARD_ROMSIZE_KB_8192
-	select HAVE_ACPI_TABLES
-	select HAVE_OPTION_TABLE
-
-config MAINBOARD_DIR
-	string
-	default "intel/minnowmax"
-
-config MAINBOARD_PART_NUMBER
-	string
-	default "Minnow Max"
-
-config MAX_CPUS
-	int
-	default 16
-
-config FSP_FILE
-	string
-	default "../intel/fsp/baytrail/BAYTRAIL_FSP.fd"
-
-config CBFS_SIZE
-	hex
-	default 0x00300000
-
-config ENABLE_FSP_FAST_BOOT
-	bool
-	depends on HAVE_FSP_BIN
-	default y
-
-config VIRTUAL_ROM_SIZE
-	hex
-	depends on ENABLE_FSP_FAST_BOOT
-	default 0x800000
-
-config POST_DEVICE
-	bool
-	default n
-
-config VGA_BIOS
-	bool
-	default y if FSP_PACKAGE_DEFAULT
-
-endif # BOARD_INTEL_MINNOWMAX
diff --git a/src/mainboard/intel/minnowmax/Kconfig.name b/src/mainboard/intel/minnowmax/Kconfig.name
deleted file mode 100644
index abe9225960..0000000000
--- a/src/mainboard/intel/minnowmax/Kconfig.name
+++ /dev/null
@@ -1,2 +0,0 @@
-config BOARD_INTEL_MINNOWMAX
-	bool "Minnow Max"
diff --git a/src/mainboard/intel/minnowmax/Makefile.inc b/src/mainboard/intel/minnowmax/Makefile.inc
deleted file mode 100644
index 3074df2138..0000000000
--- a/src/mainboard/intel/minnowmax/Makefile.inc
+++ /dev/null
@@ -1,17 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013 Google Inc.
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-ramstage-y += gpio.c
-ramstage-y += irqroute.c
diff --git a/src/mainboard/intel/minnowmax/acpi/ec.asl b/src/mainboard/intel/minnowmax/acpi/ec.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/ec.asl
+++ /dev/null
diff --git a/src/mainboard/intel/minnowmax/acpi/mainboard.asl b/src/mainboard/intel/minnowmax/acpi/mainboard.asl
deleted file mode 100644
index b032ee189d..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/mainboard.asl
+++ /dev/null
@@ -1,20 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2011 Google Inc.
- *
- * This program is free software; you can redistribute it and/or
- * modify it under the terms of the GNU General Public License as
- * published by the Free Software Foundation; version 2 of
- * the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-Device (PWRB)
-{
-	Name(_HID, EisaId("PNP0C0C"))
-}
diff --git a/src/mainboard/intel/minnowmax/acpi/superio.asl b/src/mainboard/intel/minnowmax/acpi/superio.asl
deleted file mode 100644
index e69de29bb2..0000000000
--- a/src/mainboard/intel/minnowmax/acpi/superio.asl
+++ /dev/null
diff --git a/src/mainboard/intel/minnowmax/acpi_tables.c b/src/mainboard/intel/minnowmax/acpi_tables.c
deleted file mode 100644
index fe95a3106c..0000000000
--- a/src/mainboard/intel/minnowmax/acpi_tables.c
+++ /dev/null
@@ -1,48 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2012 Google Inc.
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <types.h>
-#include <arch/acpi.h>
-#include <arch/ioapic.h>
-#include <arch/smp/mpspec.h>
-#include <device/device.h>
-#include <device/pci.h>
-#include <soc/acpi.h>
-#include <soc/nvs.h>
-#include <soc/iomap.h>
-
-void acpi_create_gnvs(global_nvs_t *gnvs)
-{
-	acpi_init_gnvs(gnvs);
-
-	/* No TPM Present */
-	gnvs->tpmp = 0;
-
-}
-
-unsigned long acpi_fill_madt(unsigned long current)
-{
-	/* Local APICs */
-	current = acpi_create_madt_lapics(current);
-
-	/* IOAPIC */
-	current += acpi_create_madt_ioapic((acpi_madt_ioapic_t *) current,
-				2, IO_APIC_ADDR, 0);
-
-	current = acpi_madt_irq_overrides(current);
-
-	return current;
-}
diff --git a/src/mainboard/intel/minnowmax/board_info.txt b/src/mainboard/intel/minnowmax/board_info.txt
deleted file mode 100644
index 5af79f8de4..0000000000
--- a/src/mainboard/intel/minnowmax/board_info.txt
+++ /dev/null
@@ -1,4 +0,0 @@
-Category: sbc
-ROM protocol: SPI
-Flashrom support: y
-Release year: 2014
diff --git a/src/mainboard/intel/minnowmax/cmos.layout b/src/mainboard/intel/minnowmax/cmos.layout
deleted file mode 100644
index 4cb5106191..0000000000
--- a/src/mainboard/intel/minnowmax/cmos.layout
+++ /dev/null
@@ -1,108 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2007-2008 coresystems GmbH
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-# -----------------------------------------------------------------
-entries
-
-# -----------------------------------------------------------------
-# Status Register A
-# -----------------------------------------------------------------
-# Status Register B
-# -----------------------------------------------------------------
-# Status Register C
-#96           4       r       0        status_c_rsvd
-#100          1       r       0        uf_flag
-#101          1       r       0        af_flag
-#102          1       r       0        pf_flag
-#103          1       r       0        irqf_flag
-# -----------------------------------------------------------------
-# Status Register D
-#104          7       r       0        status_d_rsvd
-#111          1       r       0        valid_cmos_ram
-# -----------------------------------------------------------------
-# Diagnostic Status Register
-#112          8       r       0        diag_rsvd1
-
-# -----------------------------------------------------------------
-0          120       r       0        reserved_memory
-#120        264       r       0        unused
-
-# -----------------------------------------------------------------
-# RTC_BOOT_BYTE (coreboot hardcoded)
-384          1       e       4        boot_option
-388          4       h       0        reboot_counter
-#390          2       r       0        unused?
-
-# -----------------------------------------------------------------
-# coreboot config options: console
-#392          3       r       0        unused
-395          4       e       6        debug_level
-#399          1       r       0        unused
-
-# coreboot config options: cpu
-400          1       e       2        hyper_threading
-#401          7       r       0        unused
-
-# coreboot config options: southbridge
-408          1       e       1        nmi
-409          2       e       7        power_on_after_fail
-411          2       e       8        use_xhci_over_ehci
-#413          3       r       0        unused
-
-# MRC Scrambler Seed values
-896         32        r       0        mrc_scrambler_seed
-928         32        r       0        mrc_scrambler_seed_s3
-
-# coreboot config options: check sums
-984         16       h       0        check_sum
-#1000        24       r       0        amd_reserved
-
-#save timestamps in pre-ram boot areas
-1720        64       h       0        timestamp_value1
-1784        64       h       0        timestamp_value2
-1848        64       h       0        timestamp_value3
-1912        64       h       0        timestamp_value4
-1976        64       h       0        timestamp_value5
-
-# -----------------------------------------------------------------
-
-enumerations
-
-#ID value   text
-1     0     Disable
-1     1     Enable
-2     0     Enable
-2     1     Disable
-4     0     Fallback
-4     1     Normal
-6     0     Emergency
-6     1     Alert
-6     2     Critical
-6     3     Error
-6     4     Warning
-6     5     Notice
-6     6     Info
-6     7     Debug
-6     8     Spew
-7     0     Disable
-7     1     Enable
-7     2     Keep
-8     0     EHCI
-8     1     XHCI
-8     2     Default
-# -----------------------------------------------------------------
-checksums
-
-checksum 392 415 984
diff --git a/src/mainboard/intel/minnowmax/devicetree.cb b/src/mainboard/intel/minnowmax/devicetree.cb
deleted file mode 100644
index 873b5898e7..0000000000
--- a/src/mainboard/intel/minnowmax/devicetree.cb
+++ /dev/null
@@ -1,93 +0,0 @@
-##
-## This file is part of the coreboot project.
-##
-## Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
-## Copyright (C) 2014 Intel Corporation
-##
-## This program is free software; you can redistribute it and/or modify
-## it under the terms of the GNU General Public License as published by
-## the Free Software Foundation; version 2 of the License.
-##
-## This program is distributed in the hope that it will be useful,
-## but WITHOUT ANY WARRANTY; without even the implied warranty of
-## MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
-## GNU General Public License for more details.
-##
-
-chip soc/intel/fsp_baytrail
-
-	#### ACPI Register Settings ####
-	register "fadt_pm_profile"         = "PM_UNSPECIFIED"
-	register "fadt_boot_arch"          = "ACPI_FADT_LEGACY_FREE"
-
-	#### FSP register settings ####
-	register "PcdSataMode"             = "SATA_MODE_AHCI"
-	register "PcdMrcInitSPDAddr1"      = "SPD_ADDR_DEFAULT"
-	register "PcdMrcInitSPDAddr2"      = "SPD_ADDR_DEFAULT"
-	register "PcdMrcInitMmioSize"      = "MMIO_SIZE_DEFAULT"
-	register "PcdeMMCBootMode"         = "EMMC_FOLLOWS_DEVICETREE"
-	register "PcdIgdDvmt50PreAlloc"    = "IGD_MEMSIZE_DEFAULT"
-	register "PcdApertureSize"         = "APERTURE_SIZE_DEFAULT"
-	register "PcdGttSize"              = "GTT_SIZE_DEFAULT"
-	register "PcdLpssSioEnablePciMode" = "LPSS_PCI_MODE_DEFAULT"
-	register "AzaliaAutoEnable"        = "AZALIA_FOLLOWS_DEVICETREE"
-	register "LpeAcpiModeEnable"       = "LPE_ACPI_MODE_DISABLED"
-	register "IgdRenderStandby"        = "IGD_RENDER_STANDBY_ENABLE"
-	register "EnableMemoryDown"        = "MEMORY_DOWN_ENABLE"
-	register "DRAMSpeed"               = "DRAM_SPEED_1066MHZ"
-	register "DRAMType"                = "DRAM_TYPE_DDR3L"
-	register "DIMM0Enable"             = "DIMM0_ENABLE"
-	register "DIMM1Enable"             = "DIMM1_DISABLE"
-	register "DIMMDWidth"              = "DIMM_DWIDTH_X16"
-	register "DIMMDensity"             = "DIMM_DENSITY_2G_BIT" # Setting for 1GB board - modified runtime for 2GB board in romstage.c to DIMM_DENSITY_4G_BIT
-	register "DIMMBusWidth"            = "DIMM_BUS_WIDTH_64BIT"
-	register "DIMMSides"               = "DIMM_SIDES_1RANK"
-	register "DIMMtCL"                 = "11"
-	register "DIMMtRPtRCD"             = "11"
-	register "DIMMtWR"                 = "12"
-	register "DIMMtWTR"                = "6"
-	register "DIMMtRRD"                = "6"
-	register "DIMMtRTP"                = "6"
-	register "DIMMtFAW"                = "20"
-
-	device cpu_cluster 0 on
-		device lapic 0 on end
-	end
-
-	device domain 0 on
-		device pci 00.0 on end	# 8086 0F00 - SoC router		-
-		device pci 02.0 on end	# 8086 0F31 - GFX				micro HDMI
-		device pci 03.0 off end # 8086 0F38 - MIPI				-
-
-		device pci 10.0 off end	# 8086 0F14 - EMMC Port			-
-		device pci 11.0 off end	# 8086 0F15 - SDIO Port			-
-		device pci 12.0 on end	# 8086 0F16 - SD Port			MicroSD on SD3
-		device pci 13.0 on end	# 8086 0F23 - SATA AHCI			Onboard & HSEC
-		device pci 14.0 on end	# 8086 0F35 - USB XHCI - Onboard & HSEC  - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
-		device pci 15.0 on end	# 8086 0F28 - LP Engine Audio	LSEC
-		device pci 17.0 off end	# 8086 0F50 - MMC Port			-
-		device pci 18.0 on end	# 8086 0F40 - SIO - DMA			-
-		device pci 18.1 off end	# 8086 0F41 -   I2C Port 1 (0)	-
-		device pci 18.2 on end	# 8086 0F42 -   I2C Port 2 (1)	- (testpoints)
-		device pci 18.3 off end	# 8086 0F43 -   I2C Port 3 (2)	-
-		device pci 18.4 off end	# 8086 0F44 -   I2C Port 4 (3)	-
-		device pci 18.5 off end	# 8086 0F45 -   I2C Port 5 (4)	-
-		device pci 18.6 on end	# 8086 0F46 -   I2C Port 6 (5)	LSEC
-		device pci 18.7 on end	# 8086 0F47 -   I2C Port 7 (6)	HSEC
-		device pci 1a.0 on end	# 8086 0F18 - TXE				-
-		device pci 1b.0 off end	# 8086 0F04 - HD Audio			-
-		device pci 1c.0 on end	# 8086 0F48 - PCIe Port 1 (0)	Must remain on
-		device pci 1c.1 on end	# 8086 0F4A - PCIe Port 2 (1)	Onboard GBE (some models)
-		device pci 1c.2 on end	# 8086 0F4C - PCIe Port 3 (2)	Onboard GBE
-		device pci 1c.3 on end	# 8086 0F4E - PCIe Port 4 (3)	HSEC
-		device pci 1d.0 on end	# 8086 0F34 - USB EHCI - Enabling both EHCI and XHCI will default to EHCI if not changed at runtime
-		device pci 1e.0 on end	# 8086 0F06 - SIO - DMA			-
-		device pci 1e.1 on end	# 8086 0F08 -   PWM 1			LSEC
-		device pci 1e.2 on end	# 8086 0F09 -   PWM 2			LSEC
-		device pci 1e.3 on end	# 8086 0F0A -   HSUART 1		LSEC
-		device pci 1e.4 on end	# 8086 0F0C -   HSUART 2		LSEC
-		device pci 1e.5 on end	# 8086 0F0E -   SPI				LSEC
-		device pci 1f.0 on end	# 8086 0F1C - LPC bridge		No connector
-		device pci 1f.3 on end	# 8086 0F12 - SMBus 0			SPC
-	end
-end
diff --git a/src/mainboard/intel/minnowmax/dsdt.asl b/src/mainboard/intel/minnowmax/dsdt.asl
deleted file mode 100644
index bea6af7973..0000000000
--- a/src/mainboard/intel/minnowmax/dsdt.asl
+++ /dev/null
@@ -1,54 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#define INCLUDE_LPE  1
-#define INCLUDE_SCC  1
-#define INCLUDE_EHCI 1
-#define INCLUDE_XHCI 1
-#define INCLUDE_LPSS 1
-
-
-#include <arch/acpi.h>
-DefinitionBlock(
-	"dsdt.aml",
-	"DSDT",
-	0x02,		// DSDT revision: ACPI v2.0 and up
-	OEM_ID,
-	ACPI_TABLE_CREATOR,
-	0x20110725	// OEM revision
-)
-{
-	// Some generic macros
-	#include <soc/intel/fsp_baytrail/acpi/platform.asl>
-
-	// global NVS and variables
-	#include <soc/intel/fsp_baytrail/acpi/globalnvs.asl>
-
-	#include <cpu/intel/common/acpi/cpu.asl>
-
-	Scope (\_SB) {
-		Device (PCI0)
-		{
-			#include <soc/intel/fsp_baytrail/acpi/southcluster.asl>
-		}
-	}
-
-	/* Chipset specific sleep states */
-	#include <southbridge/intel/common/acpi/sleepstates.asl>
-
-	#include "acpi/mainboard.asl"
-}
diff --git a/src/mainboard/intel/minnowmax/fadt.c b/src/mainboard/intel/minnowmax/fadt.c
deleted file mode 100644
index 4194bfc324..0000000000
--- a/src/mainboard/intel/minnowmax/fadt.c
+++ /dev/null
@@ -1,29 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2013-2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <arch/acpi.h>
-#include <soc/acpi.h>
-
-void acpi_create_fadt(acpi_fadt_t *fadt, acpi_facs_t *facs, void *dsdt)
-{
-	acpi_header_t *header = &(fadt->header);
-
-	acpi_fill_in_fadt(fadt, facs, dsdt);
-
-	/* Platform specific customizations go here */
-
-	header->checksum = acpi_checksum((void *) fadt, sizeof(acpi_fadt_t));
-}
diff --git a/src/mainboard/intel/minnowmax/gpio.c b/src/mainboard/intel/minnowmax/gpio.c
deleted file mode 100644
index b0f78c8b57..0000000000
--- a/src/mainboard/intel/minnowmax/gpio.c
+++ /dev/null
@@ -1,232 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <stdlib.h>
-#include <soc/gpio.h>
-#include "irqroute.h"
-
-/*
- * For multiplexed functions, look in EDS:
- * 10.3 Ball Name and Function by Location
- *
- * The pads list is in the BWG_VOL2 Rev1p2:
- * Note that Pad # is not the same as GPIO#
- * 37 GPIO Handling:
- *  Table 37-1. SCORE Pads List
- *  Table 37-2. SSUSORE Pads List
- */
-
-/* NCORE GPIOs */
-static const struct soc_gpio_map gpncore_gpio_map[] = {
-	GPIO_FUNC2,			// GPIO_S0_NC[00] - HDMI_HPD
-	GPIO_FUNC2,			// GPIO_S0_NC[01] - HDMI_DDCDAT
-	GPIO_FUNC2,			// GPIO_S0_NC[02] - HDMI_DDCCLK
-	GPIO_NC,			// GPIO_S0_NC[03] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[04] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[05] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[06] - No Connect
-	GPIO_FUNC2,			// GPIO_S0_NC[07] - DDI1_DDCDAT
-	GPIO_NC,			// GPIO_S0_NC[08] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[09] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[10] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[11] - No Connect
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S0_NC[12] - TP15
-	GPIO_NC,			// GPIO_S0_NC[13] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[14] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[15] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[16] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[17] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[18] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[19] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[20] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[21] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[22] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[23] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[24] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[25] - No Connect
-	GPIO_NC,			// GPIO_S0_NC[26] - No Connect
-	GPIO_END
-};
-
-/* SCORE GPIOs (GPIO_S0_SC_XX) */
-static const struct soc_gpio_map gpscore_gpio_map[] = {
-	GPIO_FUNC1,			// GPIO_S0_SC[000] - SATA_GP0
-	GPIO_FUNC1,			// GPIO_S0_SC[001] - SATA_GP1
-	GPIO_FUNC1,			// GPIO_S0_SC[002] - SATA_LED_B
-	GPIO_FUNC1,			// GPIO_S0_SC[003] - PCIE_CLKREQ_0
-	GPIO_FUNC1,			// GPIO_S0_SC[004] - PCIE_CLKREQ_1
-	GPIO_FUNC1,			// GPIO_S0_SC[005] - PCIE_CLKREQ_2
-	GPIO_FUNC1,			// GPIO_S0_SC[006] - PCIE_CLKREQ_3
-	GPIO_FUNC2,			// GPIO_S0_SC[007] - SD3_WP
-	GPIO_NC,			// GPIO_S0_SC[008] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[009] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[010] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[011] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[012] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[013] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[014] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[015] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[016] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[017] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[018] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[019] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[020] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[021] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[022] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[023] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[024] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[025] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[026] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[027] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[028] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[029] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[030] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[031] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[032] - No Connect
-	GPIO_FUNC1,			// GPIO_S0_SC[033] - SD3_CLK
-	GPIO_FUNC1,			// GPIO_S0_SC[034] - SD3_D0
-	GPIO_FUNC1,			// GPIO_S0_SC[035] - SD3_D1
-	GPIO_FUNC1,			// GPIO_S0_SC[036] - SD3_D2
-	GPIO_FUNC1,			// GPIO_S0_SC[037] - SD3_D3
-	GPIO_FUNC1,			// GPIO_S0_SC[038] - SD3_CD#
-	GPIO_FUNC1,			// GPIO_S0_SC[039] - SD3_CMD
-	GPIO_FUNC1,			// GPIO_S0_SC[040] - TP12 (SD3_1P8EN)
-	GPIO_FUNC1,			// GPIO_S0_SC[041] - TP11 (/SD3_PWREN)
-	GPIO_NC,			// GPIO_S0_SC[042] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[043] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[044] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[045] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[046] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[047] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[048] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[049] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[050] - No Connect
-	GPIO_FUNC1,			// GPIO_S0_SC[051] - PCU_SMB_DATA
-	GPIO_FUNC1,			// GPIO_S0_SC[052] - PCU_SMB_CLK
-	GPIO_FUNC1,			// GPIO_S0_SC[053] - PCU_SMB_ALERT
-	GPIO_FUNC1,			// GPIO_S0_SC[054] - ILB_8254_SPKR
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S0_SC[055] - TP8 (GPIO_S0_SC_55)
-	GPIO_FUNC0,			// GPIO_S0_SC[056] - GPIO_S0_SC_56
-	GPIO_FUNC1,			// GPIO_S0_SC[057] - PCU_UART3_TXD
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S0_SC[058] - TP9 (GPIO_S0_SC_58)
-	GPIO_FUNC0,			// GPIO_S0_SC[059] - HDMI_DCDC_ENB
-	GPIO_FUNC0,			// GPIO_S0_SC[060] - HDMI_LDSW_ENB
-	GPIO_FUNC1,			// GPIO_S0_SC[061] - PCU_UART3_RXD
-	GPIO_FUNC1,			// GPIO_S0_SC[062] - LPE_I2S_CLK
-	GPIO_FUNC1,			// GPIO_S0_SC[063] - LPE_I2S_FRM
-	GPIO_FUNC1,			// GPIO_S0_SC[064] - LPE_I2S_DATIN
-	GPIO_FUNC1,			// GPIO_S0_SC[065] - LPE_I2S_DATOUT
-	GPIO_FUNC1,			// GPIO_S0_SC[066] - SOC_SIO_SPI_CS1
-	GPIO_FUNC1,			// GPIO_S0_SC[067] - SOC_SIO_SPI_MISO
-	GPIO_FUNC1,			// GPIO_S0_SC[068] - SOC_SIO_SPI_MOSI
-	GPIO_FUNC1,			// GPIO_S0_SC[069] - SOC_SIO_SPI_CLK
-	GPIO_FUNC1,			// GPIO_S0_SC[070] - SIO_UART1_RXD
-	GPIO_FUNC1,			// GPIO_S0_SC[071] - SIO_UART1_TXD
-	GPIO_FUNC1,			// GPIO_S0_SC[072] - SIO_UART1_RTSB
-	GPIO_FUNC1,			// GPIO_S0_SC[073] - SIO_UART1_CTSB
-	GPIO_FUNC1,			// GPIO_S0_SC[074] - SIO_UART2_RXD
-	GPIO_FUNC1,			// GPIO_S0_SC[075] - SIO_UART2_TXD
-	GPIO_NC,			// GPIO_S0_SC[076] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[077] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[078] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[079] - No Connect
-	GPIO_FUNC1,			// GPIO_S0_SC[080] - TP6 (SIO_I2C1_SDA)
-	GPIO_FUNC1,			// GPIO_S0_SC[081] - TP5 (SIO_I2C1_SCL)
-	GPIO_NC,			// GPIO_S0_SC[082] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[083] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[084] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[085] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[086] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[087] - No Connect
-	GPIO_FUNC1,			// GPIO_S0_SC[088] - LSS_I2C_SDA
-	GPIO_FUNC1,			// GPIO_S0_SC[089] - LSS_I2C_SCL
-	GPIO_FUNC1,			// GPIO_S0_SC[090] - EXP_I2C_SDA
-	GPIO_FUNC1,			// GPIO_S0_SC[091] - EXP_I2C_SCL
-	GPIO_FUNC(1, PULL_UP, 20K),	// GPIO_S0_SC[092] - TP13
-	GPIO_FUNC(1, PULL_UP, 20K),	// GPIO_S0_SC[093] - TP16
-	GPIO_FUNC1,			// GPIO_S0_SC[094] - SOC_PWM0
-	GPIO_FUNC1,			// GPIO_S0_SC[095] - SOC_PWM1
-	GPIO_NC,			// GPIO_S0_SC[096] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[097] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[098] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[099] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[100] - No Connect
-	GPIO_NC,			// GPIO_S0_SC[101] - No Connect
-	GPIO_END
-};
-
-/* SSUS GPIOs (GPIO_S5) */
-static const struct soc_gpio_map gpssus_gpio_map[] = {
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[00] - SOC_GPIO_S5_0
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[01] - SOC_GPIO_S5_1
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[02] - SOC_GPIO_S5_2
-	GPIO_FUNC6,			// GPIO_S5[03] - mPCIE_WAKEB
-	GPIO_NC,			// GPIO_S5[04] - No Connect
-	GPIO_INPUT,			// GPIO_S5[05] - BOM_OP1
-					// Memory: 0=1GB 1=2GB or 4GB
-	GPIO_INPUT,			// GPIO_S5[06] - BOM_OP2
-	GPIO_INPUT,			// GPIO_S5[07] - BOM_OP3
-	GPIO_OUT_HIGH_LEGACY,		// GPIO_S5[08] - SOC_USB_HOST_EN0
-	GPIO_OUT_HIGH_LEGACY,		// GPIO_S5[09] - SOC_USB_HOST_EN1
-	GPIO_OUT_HIGH_LEGACY,		// GPIO_S5[10] - GPIO_S5_10_UNLOCK
-	GPIO_FUNC0,			// GPIO_S5[11] - SUSPWRDNACK (TP14)
-	GPIO_FUNC0,			// GPIO_S5[12] - PMC_SUSCLK0
-	GPIO_FUNC1,			// GPIO_S5[13] - PMC_SLP_S0IX (TP10)
-	GPIO_FUNC1,			// GPIO_S5[14] - GPIO_S514_J20
-	GPIO_FUNC0,			// GPIO_S5[15] - PMC_PCIE_WAKE_R
-	GPIO_FUNC0,			// GPIO_S5[16] - PMC_PWRBTN
-	GPIO_NC,			// GPIO_S5[17] - No Connect
-	GPIO_FUNC1,			// GPIO_S5[18] - LPCPD_L (TP7)
-	GPIO_FUNC0,			// GPIO_S5[19] - SOC_USB_HOST_OC0
-	GPIO_FUNC0,			// GPIO_S5[20] - SOC_USB_HOST_OC1
-	GPIO_FUNC0,			// GPIO_S5[21] - SOC_SPI_CS1B
-	GPIO_INPUT_PD,			// GPIO_S5[22] - NC or LED D2
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[23] - XDP_H_OBSDATA_A0
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[24] - XDP_H_OBSDATA_A1
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[25] - XDP_H_OBSDATA_A2
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[26] - XDP_H_OBSDATA_A3
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[27] - EXP_GPIO1
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[28] - EXP_GPIO2
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[29] - EXP_GPIO3
-	GPIO_FUNC(0, PULL_UP, 20K),	// GPIO_S5[30] - EXP_GPIO4
-	GPIO_NC,			// GPIO_S5[31] - No Connect
-	GPIO_NC,			// GPIO_S5[32] - No Connect
-	GPIO_NC,			// GPIO_S5[33] - No Connect
-	GPIO_NC,			// GPIO_S5[34] - No Connect
-	GPIO_NC,			// GPIO_S5[35] - No Connect
-	GPIO_NC,			// GPIO_S5[36] - No Connect
-	GPIO_NC,			// GPIO_S5[37] - No Connect
-	GPIO_NC,			// GPIO_S5[38] - No Connect
-	GPIO_NC,			// GPIO_S5[39] - No Connect
-	GPIO_NC,			// GPIO_S5[40] - No Connect
-	GPIO_NC,			// GPIO_S5[41] - No Connect
-	GPIO_NC,			// GPIO_S5[42] - No Connect
-	GPIO_NC,			// GPIO_S5[43] - No Connect
-	GPIO_END
-};
-
-static struct soc_gpio_config gpio_config = {
-	.ncore = gpncore_gpio_map,
-	.score = gpscore_gpio_map,
-	.ssus = gpssus_gpio_map,
-	.core_dirq = NULL,
-	.sus_dirq = NULL,
-};
-
-struct soc_gpio_config *mainboard_get_gpios(void)
-{
-	return &gpio_config;
-}
diff --git a/src/mainboard/intel/minnowmax/irqroute.c b/src/mainboard/intel/minnowmax/irqroute.c
deleted file mode 100644
index db8c512a43..0000000000
--- a/src/mainboard/intel/minnowmax/irqroute.c
+++ /dev/null
@@ -1,18 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include "irqroute.h"
-
-DEFINE_IRQ_ROUTES;
diff --git a/src/mainboard/intel/minnowmax/irqroute.h b/src/mainboard/intel/minnowmax/irqroute.h
deleted file mode 100644
index 20281b7e3f..0000000000
--- a/src/mainboard/intel/minnowmax/irqroute.h
+++ /dev/null
@@ -1,83 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC.
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#ifndef IRQROUTE_H
-#define IRQROUTE_H
-
-#include <soc/intel/fsp_baytrail/include/soc/irq.h>
-#include <soc/intel/fsp_baytrail/include/soc/pci_devs.h>
-
-/*
- *IR02h GFX      INT(A)     - PIRQ A
- *IR10h EMMC     INT(ABCD)  - PIRQ DEFG
- *IR11h SDIO     INT(A)     - PIRQ B
- *IR12h SD       INT(A)     - PIRQ C
- *IR13h SATA     INT(A)     - PIRQ D
- *IR14h XHCI     INT(A)     - PIRQ E
- *IR15h LP Audio INT(A)     - PIRQ F
- *IR17h MMC      INT(A)     - PIRQ F
- *IR18h SIO      INT(ABCD)  - PIRQ BADC
- *IR1Ah TXE      INT(A)     - PIRQ F
- *IR1Bh HD Audio INT(A)     - PIRQ G
- *IR1Ch PCIe     INT(ABCD)  - PIRQ EFGH
- *IR1Dh EHCI     INT(A)     - PIRQ D
- *IR1Eh SIO      INT(ABCD)  - PIRQ BDEF
- *IR1Fh LPC      INT(ABCD)  - PIRQ HGBC
- */
-
-/* PCIe bridge routing */
-#define BRIDGE1_DEV PCIE_DEV
-
-/* PCI bridge IRQs need to be updated in both tables and need to match */
-#define PCIE_BRIDGE_IRQ_ROUTES \
-	PCIE_BRIDGE_DEV(RP, BRIDGE1_DEV,    E, F, G, H)
-
-/* Devices set as A, A, A, A evaluate as 0, and don't get set */
-#define PCI_DEV_PIRQ_ROUTES \
-	PCI_DEV_PIRQ_ROUTE(GFX_DEV,     A, A, A, B), \
-	PCI_DEV_PIRQ_ROUTE(EMMC_DEV,    D, E, F, G), \
-	PCI_DEV_PIRQ_ROUTE(SDIO_DEV,    B, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SD_DEV,      C, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SATA_DEV,    D, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(XHCI_DEV,    E, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(LPE_DEV,     F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(MMC45_DEV,   F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SIO1_DEV,    B, A, D, C), \
-	PCI_DEV_PIRQ_ROUTE(TXE_DEV,     F, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(HDA_DEV,     G, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(BRIDGE1_DEV, E, F, G, H), \
-	PCI_DEV_PIRQ_ROUTE(EHCI_DEV,    D, A, A, A), \
-	PCI_DEV_PIRQ_ROUTE(SIO2_DEV,    B, D, E, F), \
-	PCI_DEV_PIRQ_ROUTE(PCU_DEV,     H, G, B, C)
-
-/*
- * Route each PIRQ[A-H] to a PIC IRQ[0-15]
- * Reserved: 0, 1, 2, 8, 13
- * PS2 keyboard: 12
- * ACPI/SCI: 9
- * Floppy: 6
- */
-#define PIRQ_PIC_ROUTES \
-	PIRQ_PIC(A,  3), \
-	PIRQ_PIC(B,  5), \
-	PIRQ_PIC(C,  7), \
-	PIRQ_PIC(D, 10), \
-	PIRQ_PIC(E, 11), \
-	PIRQ_PIC(F, 12), \
-	PIRQ_PIC(G, 14), \
-	PIRQ_PIC(H, 15)
-
-#endif /* IRQROUTE_H */
diff --git a/src/mainboard/intel/minnowmax/mainboard.c b/src/mainboard/intel/minnowmax/mainboard.c
deleted file mode 100644
index 0fe1259420..0000000000
--- a/src/mainboard/intel/minnowmax/mainboard.c
+++ /dev/null
@@ -1,41 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2007-2009 coresystems GmbH
- * Copyright (C) 2011 The ChromiumOS Authors.  All rights reserved.
- * Copyright (C) 2014 Sage Electronic Engineering, LLC
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <device/device.h>
-
-/*
- * mainboard_enable is executed as first thing after enumerate_buses().
- * This is the earliest point to add customization.
- */
-static void mainboard_enable(struct device *dev)
-{
-}
-
-/*
- * mainboard_final is executed as one of the last items before loading the
- * payload.
- *
- * This is the latest point to add customization.
- */
-static void mainboard_final(void *chip_info)
-{
-}
-
-struct chip_operations mainboard_ops = {
-	.enable_dev = mainboard_enable,
-	.final = mainboard_final,
-};
diff --git a/src/mainboard/intel/minnowmax/romstage.c b/src/mainboard/intel/minnowmax/romstage.c
deleted file mode 100644
index 38b7e0d6ff..0000000000
--- a/src/mainboard/intel/minnowmax/romstage.c
+++ /dev/null
@@ -1,140 +0,0 @@
-/*
- * This file is part of the coreboot project.
- *
- * Copyright (C) 2013 Google Inc.
- * Copyright (C) 2013 Sage Electronic Engineering, LLC.
- * Copyright (C) 2014 Intel Corporation
- * Copyright (C) 2018 CMR Surgical Limited
- *
- * This program is free software; you can redistribute it and/or modify
- * it under the terms of the GNU General Public License as published by
- * the Free Software Foundation; version 2 of the License.
- *
- * This program is distributed in the hope that it will be useful,
- * but WITHOUT ANY WARRANTY; without even the implied warranty of
- * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
- * GNU General Public License for more details.
- */
-
-#include <soc/romstage.h>
-#include <drivers/intel/fsp1_0/fsp_util.h>
-#include <pc80/mc146818rtc.h>
-#include <console/console.h>
-#include <soc/gpio.h>
-#include <soc/intel/fsp_baytrail/chip.h>
-#include <cpu/x86/tsc.h>
-
-/**
- * /brief mainboard call for setup that needs to be done before fsp init
- *
- */
-void early_mainboard_romstage_entry(void)
-{
-
-}
-
-/**
- * Get function disables - most of these will be done automatically
- * @param fd_mask
- * @param fd2_mask
- */
-void get_func_disables(uint32_t *fd_mask, uint32_t *fd2_mask)
-{
-
-}
-
-/**
- * /brief mainboard call for setup that needs to be done after fsp init
- *
- */
-void late_mainboard_romstage_entry(void)
-{
-
-}
-
-/* Set up the default soldered down memory config for 1GB */
-static const MEMORY_DOWN_DATA minnowmax_memory_config[] = {
-	/* 1066 */
-	{
-	.EnableMemoryDown = 1,
-	.DRAMSpeed = 1,      /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
-	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
-	.DIMM0Enable = 1,    /* DIMM 0 Enable */
-	.DIMM1Enable = 0,    /* DIMM 1 Enable */
-	.DIMMDWidth = 1,     /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
-	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
-	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
-	.DIMMSides = 0,      /* Ranks Per DIMM: 0=1rank, 1=2rank */
-	.DIMMtCL = 11,        /* tCL */
-	.DIMMtRPtRCD = 11,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
-	.DIMMtWR = 12,        /* tWR in DRAM clk  */
-	.DIMMtWTR = 6,       /* tWTR in DRAM clk */
-	.DIMMtRRD = 6,       /* tRRD in DRAM clk */
-	.DIMMtRTP = 6,       /* tRTP in DRAM clk */
-	.DIMMtFAW = 20,      /* tFAW in DRAM clk */
-	},
-	/* 1333 */
-	{
-	.EnableMemoryDown = 1,
-	.DRAMSpeed = 2,      /* DRAM Speed: 0=800, 1=1066, 2=1333, 3=1600*/
-	.DRAMType = 1,       /* DRAM Type: 0=DDR3, 1=DDR3L, 2=DDR3U, 4=LPDDR2, 5=LPDDR3, 6=DDR4*/
-	.DIMM0Enable = 1,    /* DIMM 0 Enable */
-	.DIMM1Enable = 0,    /* DIMM 1 Enable */
-	.DIMMDWidth = 1,     /* DRAM device data width: 0=x8, 1=x16, 2=x32*/
-	.DIMMDensity = 1,    /* DRAM device data density: 0=1Gb, 1=2Gb, 2=4Gb, 3=8Gb */
-	.DIMMBusWidth = 3,   /* DIMM Bus Width: 0=8bit, 1=16bit, 2=32bit, 3=64bit */
-	.DIMMSides = 0,      /* Ranks Per DIMM: 0=1rank, 1=2rank */
-	.DIMMtCL = 9,        /* tCL */
-	.DIMMtRPtRCD = 9,    /* tRP and tRCD in DRAM clk - 5:12.5ns, 6:15ns, etc. */
-	.DIMMtWR = 10,       /* tWR in DRAM clk  */
-	.DIMMtWTR = 5,       /* tWTR in DRAM clk */
-	.DIMMtRRD = 4,       /* tRRD in DRAM clk */
-	.DIMMtRTP = 5,       /* tRTP in DRAM clk */
-	.DIMMtFAW = 30,      /* tFAW in DRAM clk */
-	}
-};
-
-void romstage_fsp_rt_buffer_callback(FSP_INIT_RT_BUFFER *FspRtBuffer)
-{
-	UPD_DATA_REGION *UpdData = FspRtBuffer->Common.UpdDataRgnPtr;
-	u8 use_xhci = UpdData->PcdEnableXhci;
-	u8 gpio5 = 0;
-	int is_1333_sku;
-
-	/*
-	 * The E3827 and E3845 SKUs are fused at 1333MHz DDR3 speeds. There's
-	 * no good way of knowing the SKU'ing so frequency is used as a proxy.
-	 * The E3805, E3815, E3825, and E3826 are all <= 1460MHz while the
-	 * E3827 and E3845 are 1750MHz and 1910MHz, respectively.
-	 */
-	is_1333_sku = !!(tsc_freq_mhz() >= 1700);
-
-	printk(BIOS_INFO, "Using %d MHz DDR3 settings.\n",
-		is_1333_sku ? 1333 : 1066);
-
-	/* Set up soldered down memory parameters for 1GB */
-	UpdData->PcdMemoryParameters = minnowmax_memory_config[is_1333_sku];
-
-	/*
-	 * Minnow Max Board
-	 * Read SSUS gpio 5 to determine memory type
-	 *                    0 : 1GB SKU uses 2Gb density memory
-	 *                    1 : 2GB SKU uses 4Gb density memory
-	 *
-	 * devicetree.cb assumes 1GB SKU board
-	 */
-	configure_ssus_gpio(5, PAD_FUNC0 | PAD_PULL_DISABLE, PAD_VAL_INPUT);
-	gpio5 = read_ssus_gpio(5);
-	if (gpio5)
-		UpdData->PcdMemoryParameters.DIMMDensity
-		+= (DIMM_DENSITY_4G_BIT - DIMM_DENSITY_2G_BIT);
-	printk(BIOS_NOTICE, "%s GB Minnowboard Max detected.\n",
-			gpio5 ? "2 / 4" : "1");
-	/* Update XHCI UPD value if required */
-	get_option(&use_xhci, "use_xhci_over_ehci");
-	if ((use_xhci < 2) && (use_xhci != UpdData->PcdEnableXhci)) {
-		UpdData->PcdEnableXhci = use_xhci;
-		printk(FSP_INFO_LEVEL, "Xhci updated from CMOS:\t\t\t%s\n",
-			UpdData->PcdEnableXhci?"Enabled":"Disabled");
-	}
-}